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參數資料
| 型號： | ADSP-21MSP58BST-104 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數字信號處理 |
| 英文描述： | DSP Microcomputers |
| 中文描述： | 24-BIT, 13 MHz, OTHER DSP, PQFP100 |
| 封裝： | METRIC, PLASTIC, TQFP-100 |
| 文件頁數： | 35/40頁 |
| 文件大小： | 372K |
| 代理商： | ADSP-21MSP58BST-104 |
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ADSP-21msp58/59
REV. 0
–35–
E NVIRONME NT AL CONDIT IONS
Ambient T emperature Rating:
T
AMB
= T
CASE
– (PD
×
θ
C A
)
T
CASE
= Case T emperature in
°
C
PD = Power Dissipation in W
θ
C A
= T hermal Resistance (Case-to-Ambient)
θ
JA
= T hermal Resistance (Junction-to-Ambient)
θ
JC
= T hermal Resistance (Junction-to-Case)
Package
θ
JA
θ
JC
θ
CA
T QFP
50
°
C/W
2
°
C/W
48
°
C/W
POWE R DISSIPAT ION
T o determine total power dissipation in a specific application,
the following equation should be applied for each output:
C
×
V
DD
2
×
f
C
= load capacitance,
f
= output switching frequency.
E xample:
In an application where external data memory is used and no
other outputs are active, power dissipation is calculated as
follows:
Assumptions:
External data memory is accessed every cycle with 50% of the
address pins switching.
External data memory writes occur every other cycle with
50% of the data pins switching.
Each address and data pin has a 10 pF total load at the pin.
T he application operates at V
DD
= 5.0 V and t
CK
= 76.92 ns.
Total Power Dissipation
=
P
INT
+
(C
×
V
DD2
×
f
)
P
INT
= internal power dissipation from Power vs. Frequency
graph (Figure 25).
(
C
×
V
DD2
×
f
) is calculated for each output:
# of
Pins
×
C
×
V
DD2
×
f
Address,
DMS
Data Output,
WR
RD
CLK OUT
8
9
1
1
×
10 pF
×
10 pF
×
10 pF
×
10 pF
×
5
2
V
×
5
2
V
×
5
2
V
×
5
2
V
×
26 MHz
×
13 MHz
×
13 MHz
×
26 MHz
=
=
=
=
52 mW
30 mW
4 mW
6 mW
92 mW
T otal power dissipation for this example is P
INT
+ 92 mW.
T ypical Power Consumption
T he typical power consumption can be calculated from the fol-
lowing data, taken at 5.0 V and +25
°
C. Dynamic V
DD
data was
taken while executing 80% type 1 multifunction instructions, on
random data.
Parameter
I
DD
Digital Supply Current (Idle, Codec Powered Up)
I
DD
Digital Supply Current (Idle)
I
DD
Digital Supply Current (Dynamic, Codec Powered Up) 83 mA
I
DD
Digital Supply Current (Dynamic)
I
DD
Digital Supply Current (Powerdown)
I
CC
Analog Supply Current (Dynamic)
T yp
19 mA
13 mA
78 mA
10
μ
A
15 mA
Analog Devices recommends that the ADSP-21msp58/59
is used with a 13 MHz input clock. Below this input clock
frequency, the codec performance changes and the performance
specifications cannot be guaranteed. T he codec filter character-
istics, however, scale approximately linearly with frequency.
If the codec is disabled, then the processor can be used at any
allowed input frequency. T he power consumption of the ADSP-
21msp58/59 at these frequencies is shown in Figure 25.
65mW
37mW
35mW
29mW
21mW
20mW
70
60
50
40
30
20
10
POWER, IDLE n MODES
3
2
6
10
14
1/t
CK
– MHz
18
22
26
30
IDLEs @ 5.0V
CODEC INACTIVE
TYPICAL VALUES
IDLE (16)
IDLE (32)
IDLE (64)
IDLE (128)
P
I
N
POWER, IDLE
2
110
100
90
80
70
60
50
40
302
6
10
14
1/t
CK
– MHz
18
22
26
30
100mW
83mW
69mW
57mW
49mW
42mW
V
DD
= 5.5V
V
DD
= 4.5V
P
I
)
IDLE 0
CODEC INACTIVE
MAX VALUES
V
DD
=50V
POWER, INTERNAL
1
480mW
391mW
310mW
191mW
154mW
118mW
550
500
450
400
350
300
250
200
150
100
502
6
10
14
1/t
CK
– MHz
18
22
26
30
P
I
)
V
DD
= 5.5V
V
DD
= 4.5V
INTERNAL
(80% NOMINAL LOADING)
CODEC INACTIVE
MAX VALUES
550
500
450
400
350
300
250
200
150
100
50
V
DD
=50V
1
2
3
VALID FOR ALL TEMPERATURE GRADES.
POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS.
IDLE REFERS TO ADSP-21msp58/59 STATE OF OPERATION DURING EXECUTION OF
IDLE INSTRUCTION. DEASSERTED PINS ARE DRIVEN TO EITHER V
DD
OR GND.
POWER REFLECTS DEVICE OPERATING WITH CLKOUT DISABLED.
TYPICAL POWER DISSIPATION AT 5.0V V
DURING EXECUTION OF IDLE n
INSTRUCTION (CLOCK FREQUENCY REDUCTION). POWER REFLECTS DEVICE
OPERATING WITH CLKOUT DISABLED.
Figure 25. Power vs. Internal Processor Frequency
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