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參數資料
| 型號： | ADSP-21MSP58BST-104 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數字信號處理 |
| 英文描述： | DSP Microcomputers |
| 中文描述： | 24-BIT, 13 MHz, OTHER DSP, PQFP100 |
| 封裝： | METRIC, PLASTIC, TQFP-100 |
| 文件頁數： | 3/40頁 |
| 文件大小： | 372K |
| 代理商： | ADSP-21MSP58BST-104 |
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ADSP-21msp58/59
REV. 0
–3–
seven wait states are automatically generated. T his allows, for
example, a 38 ns ADSP-21msp58/59 to use a 250 ns EPROM
as external boot memory. Multiple programs can be selected
and loaded from the EPROM with no additional hardware. T he
on-chip program memory can also be initialized through the
HIP.
T he ADSP-21msp58/59 features a general purpose flag output
whose state is controlled through software. You can use this
output to signal an event to an external device. In addition, the
data input and output pins on SPORT 1 can be alternatively
configured as an input and an output flag.
A programmable interval timer can generate periodic interrupts.
A 16-bit count register (T COUNT ) is decremented every
n
cycles, where
n–1
is a scaling value stored in an 8-bit register
(T SCALE). When the value of the count register reaches zero,
an interrupt is generated and the count register is reloaded from
a 16-bit period register (T PERIOD).
T he ADSP-21msp58/59 instruction set provides flexible data
moves and multifunction (one or two data moves with a compu-
tation) instructions. Every instruction can be executed in a
single processor cycle. T he ADSP-21msp58/59 uses an alge-
braic syntax for ease of coding and readability. A comprehensive
set of development tools supports program development.
Serial Ports
T he ADSP-21msp58/59 processors include two synchronous se-
rial ports (SPORT 0 and SPORT 1) for serial communications
and multiprocessor communication.
Here is a brief list of the capabilities of the ADSP-21msp58/59
SPORT s. Refer to the
ADSP-2100 Family User’s Manual
for fur-
ther details.
SPORT s are bidirectional with a separate, double-buffered
transmit and receive section.
SPORT s can use an external serial clock or generate their own
clock internally.
SPORT s have independent framing for the transmit and
receive sections. Sections run in a frameless mode or with
frame synchronization signals internally or externally gener-
ated. Frame sync signals are programmed to be active high or
low, with either of two pulse widths and timings.
SPORT s support serial data word lengths from 3 to 16 bits
and provide optional A-law and
μ
-law companding according
to CCIT T recommendation G.711.
SPORT s receive and transmit sections generate separate
interrupts when the SPORT s are ready to read or write new
data.
SPORT s can receive and transmit an entire circular buffer of
data with only one overhead cycle per data word (Autobuffering
Mode). An interrupt is generated after a complete data buffer
transfer.
SPORT 0 has a multichannel interface to selectively receive
and transmit a 24- or 32-word, time-division multiplexed
serial bit stream.
SPORT 1 can be reconfigured as two external interrupt inputs
(
IRQ0
and
IRQ1
) and the Flag In and Flag Out signals (FI,
FO). T he internally generated serial clock may still be used in
this configuration.
Pin Descriptions
T he ADSP-21msp58 and ADSP-21msp59 are available in a
100-lead T QFP package. T able I contains the pin descriptions.
T able I. ADSP-21msp58/59 Pin List
Pin
Group
Name
#
of
Pins Output Function
Input/
Digital Pin
s
Address
14
O
Address output for program,
dataand boot memory spaces
Data I/O pins for program
and data memories. Input
only for boot memory space,
with two MSBs used as boot
space addresses.
Processor reset input
External interrupt request #2
External bus request input
External bus grant output
External program memory select
External data memory select
Boot memory select
External memory read enable
External memory write enable
Memory map select
Data
24
I/O
RESET
IRQ2
BR
BG
PMS
DMS
BMS
RD
WR
MMAP
CLK IN,
X T AL
1
1
1
1
1
1
1
1
1
1
I
I
I
O
O
O
O
O
O
I
2
I
External clock or quartz crystal
input
Processor clock output
HIP acknowledge output
HIP select input
Boot mode select
(0 = Standard
EPROM Booting, 1 = HIP
Booting)
Bus strobe select
(0 =
RD
/
WR
,
1 = RW/
DS
)
HIP address/data mode select
(0 = Separate, 1 = Multiplexed)
HIP read strobe
or
read/write
select
HIP write strobe
or
host data
strobe select
CLK OUT
HACK
HSEL
BMODE
1
1
1
1
O
O
I
I
HMD0
1
I
HMD1
1
I
HRD
/HRW
1
I
HWR
/
HDS
1
I
HD7–0/
HAD7–0
8
I/O
HIP data
or
HIP data and
address
Host address 2
or
address latch
enable
HA2/ALE
1
I
HA1–0/
(unused)
SPORT 0
2
5
I
I/O
Host address 1 and 0 inputs
Serial port 0 pins
(TFS0, RFS0,
DT0, DR0, SCLK0)
Serial port 1 pins
(TFS1, RFS1,
DT1, DR1, SCLK1)
SPORT 1
5
I/O
or
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