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參數(shù)資料
| 型號： | ADSP-21MSP58BST-104 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | DSP Microcomputers |
| 中文描述： | 24-BIT, 13 MHz, OTHER DSP, PQFP100 |
| 封裝： | METRIC, PLASTIC, TQFP-100 |
| 文件頁數(shù)： | 17/40頁 |
| 文件大小： | 372K |
| 代理商： | ADSP-21MSP58BST-104 |
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ADSP-21msp58/59
REV. 0
–17–
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HSR7
0x3FE7
ADSP-21msp58/59 HDR0 Write
ADSP-21msp58/59 HDR1 Write
ADSP-21msp58/59 HDR2 Write
ADSP-21msp58/59 HDR3 Write
ADSP-21msp58/59 HDR4 Write
ADSP-21msp58/59 HDR5 Write
Overwrite Mode
Software Reset
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HSR6
0x3FE6
ADSP-21msp58/59 HDR5 Write
ADSP-21msp58/59 HDR4 Write
ADSP-21msp58/59 HDR3 Write
ADSP-21msp58/59 HDR2 Write
ADSP-21msp58/59 HDR1 Write
ADSP-21msp58/59 HDR0 Write
Host HDR0 Write
Host HDR1 Write
Host HDR2 Write
Host HDR3 Write
Host HDR4 Write
Host HDR5 Write
Control Registers
ADSP-21msp58/59 E X T E NDE D INST RUCT ION SE T
T he ADSP-21msp58/59 has a number of additional instruc-
tions beyond the standard ADSP-2100 Family instruction set.
T hese additional instructions and mathematical operations are
described below.
Slow IDLE
Slow IDLE allows slowing the processor’s internal clock by a
factor of 16, 32, 64, or 128 during IDLE. T he instruction
source code is specified as follows:
Syntax:
IDLE (n);
Permissible Values for n
16, 32, 64, 128
E xamples:
IDLE;
IDLE (16);
Description:
T he IDLE instruction causes the processor to
wait indefinitely in a low power state until an in-
terrupt occurs. When an unmasked interrupt oc-
curs, it is serviced; execution then continues with
the instruction following the IDLE instruction.
T he optional value provides a “slow idle” fea-
ture; slowing the clock down by the factor set
with the value.
Interrupt E nable and Disable Instructions
T he ADSP-21msp58/59 supports an interrupt enable instruc-
tion and interrupt disable instruction. Interrupts are enabled by
default at reset. T he interrupt enable instruction source code is
specified as follows:
INST RUCT ION SE T DE SCRIPT ION
T he ADSP-21msp58/59 assembly language instruction set has
an algebraic syntax that was designed for ease of coding and
readability. T he assembly language, which takes full advantage
of the processor’s unique architecture, offers the following
benefits:
T he algebraic syntax eliminates the need to remember cryptic
assembler mnemonics. For example, a typical arithmetic add
instruction, such as AR = AX 0 + AY0, resembles a simple
equation.
Every instruction assembles into a single 24-bit word and
executes in a single cycle.
T he syntax is a superset of the ADSP-2100 Family assembly
language and is completely source and object code compatible
with other family members. Programs may, however, need to
be relocated to utilize internal memory and conform to the
ADSP-21msp58/59 interrupt vector and reset vector map.
Sixteen condition codes are available. For conditional jump,
call, return, or arithmetic instructions, the condition can be
checked and the operation executed in the same instruction
cycle.
Multifunction instructions allow parallel execution of an
arithmetic instruction with up to two fetches and one write to
processor memory space during a single instruction cycle.
Consult the
ADSP-2100 Family User’s Manual
for a complete
description of the syntax and an instruction set reference.
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