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參數資料
| 型號： | ADSP-21MSP58BST-104 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數字信號處理 |
| 英文描述： | DSP Microcomputers |
| 中文描述： | 24-BIT, 13 MHz, OTHER DSP, PQFP100 |
| 封裝： | METRIC, PLASTIC, TQFP-100 |
| 文件頁數： | 18/40頁 |
| 文件大小： | 372K |
| 代理商： | ADSP-21MSP58BST-104 |
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REV. 0
–18–
ADSP-21msp58/59
Syntax:
Description:
Executing the ENA INT S instruction allows all
unmasked interrupts to be serviced again.
T he interrupt disable instruction source code is specified as
follows:
Syntax:
DIS INT S;
Description:
Reset enables interrupt servicing. Executing the
DIS INT S instruction causes all interrupts to be
masked without changing the contents of the
IMASK register. Disabling interrupts does not
affect the autobuffer circuitry, which will operate
normally whether or not interrupts are enabled.
T he disable interrupt instruction masks all user
interrupts including the powerdown interrupt.
ENA INT S;
E xtended ALU and Multiplier Operations
T he following extended computation operations are available
only on the ADSP-21msp58/59 processor. T he term “base in-
struction set” refers to the computations and instructions avail-
able on all ADSP-21xx processors.
Additional Constants for ALU Operations
A new set of numerical constants may be used in all nonmulti-
function ALU operations (except DIVS and DIVQ) using both
X and Y operands. T he instruction source code is specified as
follows:
Syntax:
[IF condition]
AR
= xop function
yop
AF
Permissible xops
AX 0, AX 1, AR, MR0, MR1, MR2, SR0, SR1
Permissible functions
ADD/ADD with CARRY, SUBT RACT X –Y/SUBT RACT X –
Y with BORROW, SUBT RACT Y–X /SUBT RACT Y–X with
BORROW, AND, OR, X OR
Permissible yops (base instruction set)
AY0, AY1, AF
Permissible yops and constants (extended instruction set)
AY0, AY1, AF, 0, 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024,
2048, 4096, 8192, 16384, 32767, –2, –3, –5, –9, –17, –33, –65,
–129, –257, –513, –1025, –2049, –4097, –8193, –16385, –32768
E xamples:
AR = AR+1;
AR = MR1 - 33;
IF GT AF = AX 1 OR 16;
Description:
T est the optional condition and, if true, perform
the specified function. If false then perform a no-
operation. Omitting the condition performs the
function unconditionally. T he operands are con-
tained in the data registers specified in the in-
struction or optionally a constant may be used.
constant
Additional Constants for ALU PASS Operation
A new set of numerical constants may be used in the PASS in-
struction. T he instruction source code is specified as follows:
Syntax:
[IF condition]
AR
= pass
AF
Permissible yops (base instruction set)
AY0, AY1, AF
Permissible yops and constants (extended instruction set)
AY0, AY1, AF, 0, 1, 2, 3, 4, 5, 7, 8, 9, 15, 16, 17, 31, 32, 33,
63, 64, 65, 127, 128, 129, 255, 256, 257, 511, 512, 513, 1023,
yop
constant
1024, 1025, 2047, 2048, 2049, 4095, 4096, 4097, 8191, 8192,
8193, 16383, 16384, 16385, 32766, 32767, –1, –2, –3, –4, –5,
–6, –8, –9, –10, –16, –17, –18, –32, –33, –34, –64, –65, –66, –128,
–129, –130, –256, –257, –258, –512, –513, –514, –1024, –1025,
–1026, –2048, –2049, –2050, –4096, –4097, –4098, –8192, –8193,
–8194, –16384, –16385, –16386, –32767, –32768
E xamples:
IF GE AR = PASS AY0;
IF EQ AF = PASS –1025;
Description:
T est the optional condition and, if true, pass the
source operand unmodified through the ALU
block and store in the destination location. If the
condition is not true, perform a no-operation.
Omitting the condition performs the
pass
uncon-
ditionally. T he source operand is contained in
the data registers specified in the instruction or
optional constant.
T he PASS instruction performs the transfer to the
AR register and affect the status flag; this instruc-
tion is different from a register move operation
which does not affect any status flags. PASS 0 is
one method of clearing AR. PASS 0 can also be
combined in a multifunction instruction in con-
junction with memory reads and writes to clear AR.
Note:
T he ALU status flags (in the AST AT register)
are not defined for the execution of this instruc-
tion when using the constant values other than 0,
1, and –1.
ALU Bit Operations
T he additional constants for ALU operations allow you to code
bit test, set, clear, and toggle operations through careful choice
of the constant and ALU function. For streamlined programming,
the source code for these operations can also be specified as:
Syntax:
[IF condition]
AR
AF
=
T ST BIT n of xop;
SET BIT n of xop;
CLBIT n of xop;
T GBIT n of xop;
Permissible xops
AX 0, AX 1, AR, MR0, MR1, MR2, SR0, SR1
Permissible n Values (0 = LSB
)
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
E xamples:
AF=T ST BIT 5 of AR;
IF NE JUMP SET ;
/* JUMP T O SET IF BIT IS SET */
Definitions of Operations
T ST BIT is an AND operation with a 1 in the selected bit
SET BIT is an OR operation with a 1 in the selected bit
CLBIT is an AND operation with a 0 in the selected bit
T GBIT is an X OR operation with a 1 in the selected bit
Result-Free ALU Operations
T he result-free ALU operations allow the generation of condi-
tion flags based on an ALU operation but discard the result.
T he source code for the instruction is specified as follows:
Syntax:
NONE = <ALU>;
where <ALU> is any unconditional ALU operation
of the 21xx
base instruction set
(except DIVS or DIVQ). (Note that the addi-
tional constant ALU operations of the ADSP-2171/2181 ex-
tended instruction set are not allowed.)
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