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參數資料
| 型號： | ADSP-21MSP58BST-104 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數字信號處理 |
| 英文描述： | DSP Microcomputers |
| 中文描述： | 24-BIT, 13 MHz, OTHER DSP, PQFP100 |
| 封裝： | METRIC, PLASTIC, TQFP-100 |
| 文件頁數： | 5/40頁 |
| 文件大小： | 372K |
| 代理商： | ADSP-21MSP58BST-104 |
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ADSP-21msp58/59
REV. 0
–5–
T able II. Interrupt Priority & Interrupt Vector Addresses
Interrupt Vector
Address (Hex)
Source of Interrupt
Reset (or Power-Up with PUCR = 1)
Powerdown (Nonmaskable)
IRQ2
HIP Write
HIP Read
SPORT 0 T ransmit
SPORT 0 Receive
Analog Interface T ransmit
Analog Interface Receive
SPORT 1 T ransmit or (
IRQ1
)
SPORT 1 Receive or (
IRQ0
)
T imer
0000 (
Highest Priority
)
002C
0004
0008
000C
0010
0014
0018
001C
0020
0024
0028 (
Lowest Priority
)
Interrupts can be masked or unmasked with the IMASK regis-
ter. Individual interrupt requests are logically ANDed with the
bits in IMASK ; the highest priority unmasked interrupt is then
selected. T he powerdown interrupt is non-maskable.
T he interrupt control register, ICNT L, allows the external in-
terrupts to be set as either edge- or level-sensitive. Interrupt ser-
vice routines can either be nested (with higher priority interrupts
taking precedence) or be processed sequentially (with only one
interrupt service active at a time).
T he interrupt force and clear register, IFC, is a write-only regis-
ter used to force an interrupt or clear a pending edge-sensitive
interrupt.
On-chip stacks preserve the processor status and are automati-
cally maintained during interrupt handling. T he stack is twelve
levels deep to allow interrupt nesting.
Register bit values shown in Figure 2 are the default bit values
after reset. If no values are shown, the bits are indeterminate at
reset. Reserved bits are shown in gray; these bits should always
be written with zeros.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Timer
SPORT1 Receive or IRQ0
SPORT1 Transmit or IRQ1
Analog Receive
Analog Transmit
SPORT0 Receive
SPORT0 Transmit
IRQ2
1 = enable, 0 = disable
INTERRUPT CLEAR
IRQ2
SPORT0 Transmit
SPORT0 Receive
Analog Transmit
Analog Receive
SPORT1 Transmit or IRQ1
SPORT1 Receive or IRQ0
Timer
INTERRUPT FORCE
IFC
0
0
0
0
0
0
0
0
0
0
9
8
7
6
5
4
3
2
1
0
Timer
IRQ0 or SPORT1 Receive
IRQ1 or SPORT1 Transmit
Analog Receive
Analog Transmit
1 = enable, 0 = disable
IRQ2
HIP Write
HIP Read
SPORT0 Transmit
SPORT0 Receive
IMASK
4
3
2
1
0
0
ICNTL
IRQ0 Sensitivity
IRQ1 Sensitivity
IRQ2 Sensitivity
Interrupt Nesting
1 = enable, 0 = disable
1 = edge
0 = level
Figure 2. Interrupt Registers
T he following instructions allow global enable or disable servic-
ing of the interrupts (including powerdown), regardless of the
state of IMASK . Disabling the interrupts does not affect
autobuffering.
ENA INT S;
DIS INT S;
Interrupt servicing is enabled on processor reset.
System Interface
Figure 3 shows a basic system configuration with the ADSP-
21msp58/59, two serial devices, a host processor, a boot
EPROM, optional external program and data memories, and an
analog interface. Up to 15K words of data memory and 16K
words of program memory can be supported. Programmable
wait state generation allows the processor to interface easily to
slow memories. T he ADSP-21msp58/59 also provides one ex-
ternal interrupt and two serial ports or three external interrupts
and one serial port.
Clock Signals
T he ADSP-21msp58/59 CLK IN input may be driven by a crys-
tal or by a T T L-compatible external clock signal.
T he CLK IN input may not be halted, changed in frequency
during operation, or operated at any frequency other the one
specified. Operating the ADSP-21msp58/59 at any other fre-
quency changes the analog performance, which is not tested or
supported.
If an external clock is used, it should be a T T L-compatible sig-
nal running at half the instruction rate. T he signal should be
connected to the processor’s CLK IN input; in this case, the
X T AL input must be left unconnected.
T he ADSP-21msp58/59 uses an input clock with a frequency
equal to half the instruction rate; a 13 MHz input clock yields a
38.46 ns processor cycle (which is equivalent to 26 MHz). Nor-
mally, instructions are executed in a single processor cycle.
All device timing is relative to the internal instruction clock rate,
which is indicated by the CLK OUT signal when enabled. T he
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