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參數資料
| 型號： | ADSP-21MSP58BST-104 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數字信號處理 |
| 英文描述： | DSP Microcomputers |
| 中文描述： | 24-BIT, 13 MHz, OTHER DSP, PQFP100 |
| 封裝： | METRIC, PLASTIC, TQFP-100 |
| 文件頁數： | 11/40頁 |
| 文件大?。?/td> | 372K |
| 代理商： | ADSP-21MSP58BST-104 |
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ADSP-21msp58/59
REV. 0
–11–
Autobuffering
In some applications, it is advantageous to perform block data
transfers between the analog converters and processor memory.
Analog interface autobuffering enables the automatic transfer of
data blocks directly from the ADC to on-chip processor data
memory or from on-chip processor data memory directly to the
DAC.
ADC and DAC Interrupts
T he analog interface generates two interrupts that signal either:
(1) a 16-bit, 8 kHz analog-to-digital or digital-to-analog conver-
sion has been completed, or (2) an autobuffer block transfer
has been completed (i.e., the data buffer contents have been
received or transferred).
When an analog interrupt occurs, the processor vectors to the
addresses listed in T able II,
Interrupt Priority & Interrupt Vector
Addresses
.
T he ADC receive and DAC transmit interrupts occur at an
8 kHz rate, indicating when the data registers should be ac-
cessed. On the receive side, the ADC interrupt is generated each
time an A/D conversion cycle is completed and the 16-bit data
word is available in the ADC receive register. On the transmit
side, the DAC interrupt is generated each time an D/A conver-
sion cycle is completed and the DAC transmit register is ready
for the next 16-bit data word.
Both interrupts are generated simultaneously at an 8 kHz rate,
occurring every 3250 instruction cycles with a 13 MHz internal
processor clock. T he interrupts are generated continuously,
starting when the analog interface is powered up by setting the
APWD bits (Bits 5 and 6) to one in the analog control register.
Because both interrupts occur simultaneously, only one should
be enabled (in IMASK ) to vector to a single service routine that
handles transmit and receive data. However, when using
autobuffer transfers, both interrupts should be enabled.
ADSP-21msp58/59 RE GIST E RS
Figure 9 summarizes the ADSP-21msp58/59 registers. Some
registers store values. For example, AX 0 stores an ALU oper-
and; I4 stores a DAG2 pointer. Other registers consist of control
bits and fields, or status flags. For example AST AT contains
status flags from arithmetic operations, and fields in DWAIT
control the number of wait states for different zones of data
memory.
A secondary set of registers in all computational units allows a
single-cycle context switch.
T he bit and field definitions for control and status registers are
given in the rest of this section, except IMASK , ICNT L, and
IFC, which are defined earlier in this data sheet. T he system
control register, DWAIT register, timer registers, HIP control
registers, HIP data registers, and SPORT control registers are
all mapped into data memory locations; that is, you access these
registers by reading and writing data memory locations rather
than register names. T he particular data memory address is
shown with each memory-mapped register.
Register bit values shown on the following pages are the default
bit values after reset. If no values are shown, the bits are indeter-
minate at reset. Reserved bits are shown in gray; these bits
should always be written with zeros.
POWERDOWN
CLOGIC
TX1
RX1
0x3FF2-0x3FEF
CONTROL REGISTERS
SPORT 1
MX0 MX1 MY0 MY1
MR0 MR1 MR2 MF
MAC
AX0 AX1 AY0 AY1
AF
AR
ALU
SI
SE
SB
SHIFTER
SR1
SR0
DAC
0x3FEE-0x3FEF
ADC
ANALOG INTERFACE
0x3FEC
0x3FED
0x3FFD
0x3FFC
0x3FFB
TPERIOD
TCOUNT
TSCALE
TIMER
I0
I1
I2
I3
M0
M1
M2
M3
L0
L1
L2
L3
DAG 1
0x3FFF
0x3FFE
SYSTEM CONTROL
DM WAIT CONTROL
PRROM
4K x 24
ADSONLY
DATA
SRAM
2K x 16
0x3FE0-0x3FE5
0x3FE6-0x3FE7
0x3FE8
DATA
STATUS
HMASK
INPORT
DMD BUS
16
24
14
14
PMD BUS
DMA BUS
PMA BUS
I4
I5
I6
I7
M4
M5
M6
M7
L4
L5
L6
L7
DAG 2
SSTAT
4 x 14
OWRCNTR
CNTR
IMASK
MSTAT
ASTAT
STACK
12 x 25
4 x 18
SPC
PROGRAM SEQUENCER
ICNTL
IFC
PROGRAM
SRAM
2K x 24
PX
FLAG
TX0
RX0
0x3FFA-0x3FF3
CONTROL REGISTERS
SPORT 0
Figure 9. ADSP-21msp58/59 Registers
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