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參數資料
| 型號： | ADSP-21MSP58BST-104 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數字信號處理 |
| 英文描述： | DSP Microcomputers |
| 中文描述： | 24-BIT, 13 MHz, OTHER DSP, PQFP100 |
| 封裝： | METRIC, PLASTIC, TQFP-100 |
| 文件頁數： | 7/40頁 |
| 文件大小： | 372K |
| 代理商： | ADSP-21MSP58BST-104 |
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ADSP-21msp58/59
REV. 0
–7–
T he read (
RD
) signal indicates a read operation and is used as a
read strobe or output enable signal. An external program
memory access should always be qualified with the
PMS
signal.
T he ADSP-21msp58/59 writes data from its 16-bit registers to
24-bit program memory using the PX register to provide the
lower eight bits. When the processor reads data (not instruc-
tions) from 24-bit program memory to a 16-bit data register, the
lower eight bits are placed in the PX register. T he program
memory interface can generate zero to seven wait states for ex-
ternal memory devices; the default is seven wait states after
RESET
.
Program Memory Maps
ADSP-21msp58
ADSP-21msp58 Program memory can be mapped in two ways,
depending on the state of the MMAP pin. Figure 5 shows the
two configurations. When MMAP = 0, internal RAM occupies
2K words beginning at address 0x0000; external program
memory uses the remaining 14K words beginning at address
0x0800. In this configuration, the boot loading sequence (de-
scribed in “Boot Memory Interface”) is automatically initiated
when
RESET
is released.
INTERNAL
RAM
LOADED FROM
EXTERNAL
BOOT
MEMORY
EXTERNAL
EXTERNAL
INTERNAL
RAM
NOT LOADED
0000
07FF
0800
3FFF
0000
37FF
3800
3FFF
MMAP=1
MMAP=0
Figure 5. ADSP-21msp58 Program Memory Maps
When MMAP = 1, 14K words of external program memory be-
gin at address 0x0000 and internal RAM is located in the upper
2K words, beginning at address 0x3800. In this configuration,
the boot loading sequence does not take place; execution begins
immediately after
RESET
.
ADSP-21msp59
T he ADSP-21msp59 is functionally identical to the ADSP-
21msp58. T he ADSP-21msp59 includes an additional 4K by
24-bit mask programmable ROM (see Figure 6). T he ROM
can be used to hold program instructions or data and can be
accessed twice in one instruction cycle if necessary. T he ROM
always resides at locations PM[0x0800] through PM[0x17FF]
regardless of the state of the MMAP pin. Sixteen addresses at
the end of ROM (0x17F0–0x17FF) are reserved for Analog
Devices’ use. T he ROM is enabled by setting the ROMENABLE
bit in the Data Memory Wait State control register, DM[0x3FFE].
When the ROMENABLE bit is set to 1, addressing program
memory in this range will access the on-chip ROM. When set
to 0, addressing program memory in this range will access exter-
nal program memory. T he ROMENABLE bit is set to 0 on
chip reset.
Data Memory Interface
T he data memory address bus (DMA) is 14 bits wide. T he bi-
directional external data bus is 24 bits wide, with the upper 16
bits used for data memory data (DMD) transfers.
T he data memory select (
DMS
) signal indicates access to data
memory and can be used as a chip select signal. T he write (
WR
)
signal indicates a write operation and can be used as a write
strobe. T he read (
RD
) signal indicates a read operation and can
be used as a read strobe or output enable signal.
T he ADSP-21msp58/59 supports memory-mapped I/O, with
the peripherals memory mapped into the data or program
memory address spaces and accessed by the processor in the
same manner.
Data Memory Map
T he on-chip data memory RAM resides in the 2K words begin-
ning at address 0x3000, as shown in Figure 7. In addition, data
memory locations from 0x3800 to the end of data memory at
0x3FFF are reserved. Control registers for the system, timer,
INTERNAL
RAM
LOADED FROM
EXTERNAL
BOOT
MEMORY
EXTERNAL
EXTERNAL
INTERNAL
RAM
NOT LOADED
0000
07FF
0800
3FFF
0000
07FF
0800
3FFF
ROM ENABLE = 1
MMAP = 0
EXTERNAL
EXTERNAL
INTERNAL
RAM
NOT LOADED
0000
37FF
3800
3FFF
0000
37FF
3800
3FFF
INTERNAL
MASK
PROGRAMMED
ROM
17FF
1800
RESERVED
07FF
0800
17FF
1800
INTERNAL
RAM
LOADED FROM
EXTERNAL
BOOT
MEMORY
INTERNAL
MASK
PROGRAMMED
ROM
RESERVED
ROM ENABLE = 0
MMAP = 0
ROM ENABLE = 1
MMAP = 1
ROM ENABLE = 0
MMAP = 1
EXTERNAL
Figure 6. ADSP-21msp59 Program Memory Maps
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