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參數資料
| 型號： | ADUuC7027BSTZ62-RL |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU |
| 中文描述： | 精密模擬微控制器的12位模擬I / O，ARM7TDMI的微控制器 |
| 文件頁數： | 48/92頁 |
| 文件大小： | 850K |
| 代理商： | ADUUC7027BSTZ62-RL |
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ADuC7019/20/21/22/24/25/26/27
OTHER ANALOG PERIPHERALS
DAC
The ADuC7019/7020/7021/7022/7024/7025/7026/7027
incorporate two, three, or four 12-bit voltage output DACs on-
chip depending on the model. Each DAC has a rail-to-rail voltage
output buffer capable of driving 5 kΩ/100 pF.
Rev. A | Page 48 of 92
Each DAC has three selectable ranges: 0 V to V
REF
(internal
band gap 2.5 V reference), 0 V to DAC
REF,
and 0 V to AV
DD
.
DAC
REF
is equivalent to an external reference for the DAC.
The signal range is 0 V to AV
DD
.
MMRs Interface
Each DAC is configurable independently through a control
register and a data register. These two registers are identical for
the four DACs. Only DAC0CON (see Table 26) and DAC0DAT
(see Table 27) are described in detail in this section.
DACxCON Registers
Name
DAC0CON
DAC1CON
DAC2CON
DAC3CON
Address
0xFFFF0600
0xFFFF0608
0xFFFF0610
0xFFFF0618
Default Value
0x00
0x00
0x00
0x00
Access
R/W
R/W
R/W
R/W
Table 26. DAC0CON MMR Bit Designations
Bit
Value
Name
6
5
DACCLK
Description
Reserved.
DAC Update Rate.
Set
by user to
update the DAC using Timer1.
Cleared
by user to update the DAC
using HCLK (core clock).
DAC Clear Bit.
Set
by user to enable
normal DAC operation.
Cleared
by
user to reset data register of the DAC
to zero.
Reserved. This bit should be left at 0.
Reserved. This bit should be left at 0.
DAC Range Bits.
Power-Down Mode. The DAC output
is in tri-state.
0 DAC
REF
Range.
0 V
REF
(2.5 V) Range.
0 AV
DD
Range.
4
DACCLR
3
2
1:0
00
01
10
11
DACxDAT Registers
Name
DAC0DAT
DAC1DAT
DAC2DAT
DAC3DAT
Address
0xFFFF0604
0xFFFF060C
0xFFFF0614
0xFFFF061C
Default Value
0x00000000
0x00000000
0x00000000
0x00000000
Access
R/W
R/W
R/W
R/W
Table 27. DAC0DAT MMR Bit Designations
Bit
Description
31:28
Reserved
27:16
12-bit data for DAC0
15:0
Reserved
Using the DACs
The on-chip DAC architecture consists of a resistor string DAC
followed by an output buffer amplifier, the functional
equivalent of which is shown in Figure 51.
0
R
R
R
R
R
DAC0
OUTPUT
BUFFER
BYPASSED
FROM MCU
V
REF
AV
DD
DAC
REF
Figure 51. DAC Structure
As illustrated in Figure 51, the reference source for each DAC is
user selectable in software. It can be either AV
DD
, V
REF
, or DAC
REF
.
In 0-to-AV
DD
mode, the DAC output transfer function spans
from 0 V to the voltage at the AV
DD
pin. In 0-to-DAC
REF
mode,
the DAC output transfer function spans from 0 V to the voltage at
the DAC
REF
pin. In 0-to-V
REF
mode, the DAC output transfer
function spans from 0 V to the internal 2.5 V reference, V
REF
.
The DAC output buffer amplifier features a true rail-to-rail
output stage implementation. This means that, unloaded, each
output is capable of swinging to within less than 5 mV of both
AV
DD
and ground. Moreover, the DAC’s linearity specification
(when driving a 5 kΩ resistive load to ground) is guaranteed
through the full transfer function except codes 0 to 100, and, in
0-to-AV
DD
mode only, codes 3995 to 4095.
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