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參數資料
型號： ADUuC7027BSTZ62-RL
廠商： Analog Devices, Inc.
英文描述： Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU
中文描述： 精密模擬微控制器的12位模擬I / O，ARM7TDMI的微控制器
文件頁數： 60/92頁
文件大小： 850K
代理商： ADUUC7027BSTZ62-RL
ADuC7019/20/21/22/24/25/26/27
PWMDAT0 Register
Name
PWMDAT0
Rev. A | Page 60 of 92
Address
0xFFFFFC08
Default Value
0x0000
Access
R/W
PWMDAT0 is an unsigned 16-bit register for switching period.
PWMDAT1 Register
Name
PWMDAT1
Address
0xFFFFFC0C
Default Value
0x0000
Access
R/W
PWMDAT1 is an unsigned 10-bit register for dead time.
PWMCHx Registers
Name
PWMCH0
PWMCH1
PWMCH2
Address
0xFFFFFC14
0xFFFFFC18
0xFFFFFC1C
Default Value
0x0000
0x0000
0x0000
Access
R/W
R/W
R/W
PWMCH0, PWMCH1, and PWMCH2 are channel duty cycles
for the three phases.
PWMDAT2 Register
Name
PWMDAT2
Address
0xFFFFFC24
Default Value
0x0000
Access
R/W
PWMDAT2 is an unsigned 10-bit register for PWM sync pulse
width.
GENERAL-PURPOSE INPUT/OUTPUT
The ADuC7019/7020/7021/7022/7024/7025/7026/7027 provide
40 general-purpose, bi-directional I/O (GPIO) pins. All I/O pins
are 5 V tolerant, which means that the GPIOs support an input
voltage of 5 V. In general, many of the GPIO pins have multiple
functions (see Table 39 for the pin function definitions). By
default, the GPIO pins are configured in GPIO mode.
All GPIO pins have an internal pull-up resistor (of about 100 kΩ)
and their drive capability is 1.6 mA. Note that a maximum of
20 GPIO can drive 1.6 mA at the same time. The following GPIO
have programmable pull up: P0.0, P0.4, P0.5, P0.6, P0.7, and the
8 GPIOs of P1.
The 40 GPIO are grouped in five ports, Port 0 to Port 4. Each
port is controlled by four or five MMRs, x representing the port
number.
Note that the kernel changes P0.6 from its default configuration
at reset (MRST) to GPIO mode. If MRST is used for external
circuitry, an external pull-up resistor should be used to ensure
that the level on P0.6 does not drop when the kernel switches
mode. For example, if MRST is required for power down, it can
be reconfigured in GP0CON MMR.
The input level of any GPIO can be read at any time in the
GPxDAT MMR, even when the pin is configured in a different
mode than GPIO. The PLA input are also always active.
Table 39. GPIO Pin Function Descriptions
Port
Pin
00
0
P0.0
GPIO
P0.1
GPIO
P0.2
GPIO
P0.3
GPIO
P0.4
GPIO/IRQ0
P0.5
GPIO/IRQ1
P0.6
GPIO/T1
P0.7
GPIO
1
P1.0
GPIO/T1
P1.1
GPIO
P1.2
GPIO
P1.3
GPIO
P1.4
GPIO/IRQ2
P1.5
GPIO/IRQ3
P1.6
GPIO
P1.7
GPIO
2
P2.0
GPIO
P2.1
GPIO
P2.2
GPIO
P2.3
GPIO
P2.4
GPIO
P2.5
GPIO
P2.6
GPIO
P2.7
GPIO
3
P3.0
GPIO
P3.1
GPIO
P3.2
GPIO
P3.3
GPIO
P3.4
GPIO
P3.5
GPIO
P3.6
GPIO
P3.7
GPIO
4
P4.0
GPIO
P4.1
GPIO
P4.2
GPIO
P4.3
GPIO
P4.4
GPIO
P4.5
GPIO
P4.6
GPIO
P4.7
GPIO
Configuration
01
CMP
PWM2
H
PWM2
L
TRST
PWM
TRIP
ADC
BUSY
MRST
ECLK/XCLK
1
SIN
SOUT
RTS
CTS
RI
DCD
DSR
DTR
CONV
START2
PWM0
H
PWM0
L
PWM0
H
PWM0
L
PWM1
H
PWM1
L
PWM0
H
PWM0
L
PWM1
H
PWM1
L
PWM2
H
PWM2
L
PWM
TRIP
PWM
SYNC
10
MS2
BLE
BHE
A16
MS1
MS0
AE
SIN
SCL0
SDA0
SCL1
SDA1
CLK
MISO
MOSI
CSL
SOUT
WS
RS
AE
MS0
MS1
MS2
MS3
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
11
PLAI[7]
ADC
BUSY
PLAO[1]
PLAO[2]
PLAO[3]
PLAO[4]
PLAI[0]
PLAI[1]
PLAI[2]
PLAI[3]
PLAI[4]
PLAI[5]
PLAI[6]
PLAO[0]
PLAO[5]
PLAO[6]
PLAO[7]
PLAI[8]
PLAI[9]
PLAI[10]
PLAI[11]
PLAI[12]
PLAI[13]
PLAI[14]
PLAI[15]
PLAO[8]
PLAO[9]
PLAO[10]
PLAO[11]
PLAO[12]
PLAO[13]
PLAO[14]
PLAO[15]
1
When configured in Mode 1, P0.7 is ECLK by default, or core clock output.
To configure it as a clock input, MDCLK bits in PLLCON must be set to 11.
2
The CONV
START
signal is active in all modes of P2.0.
GPxCON Registers
Name
Address
GP0CON
0xFFFFF400
GP1CON
0xFFFFF404
GP2CON
0xFFFFF408
GP3CON
0xFFFFF40C
GP4CON
0xFFFFF410
Default Value
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
Access
R/W
R/W
R/W
R/W
R/W
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