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參數資料
| 型號： | ADUuC7027BSTZ62-RL |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU |
| 中文描述： | 精密模擬微控制器的12位模擬I / O，ARM7TDMI的微控制器 |
| 文件頁數： | 83/92頁 |
| 文件大小： | 850K |
| 代理商： | ADUUC7027BSTZ62-RL |
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ADuC7019/20/21/22/24/25/26/27
HARDWARE DESIGN CONSIDERATIONS
POWER SUPPLIES
The ADuC7019/7020/7021/7022/7024/7025/7026/7027
operational power supply voltage range is 2.7 V to 3.6 V.
Separate analog and digital power supply pins (AV
DD
and
IOV
DD
, respectively) allow AV
DD
to be kept relatively free of
noisy digital signals often present on the system IOV
DD
line. In
this mode, the part can also operate with split supplies, that is,
using different voltage levels for each supply. For example, the
system can be designed to operate with an IOV
DD
voltage level
of 3.3 V while the AV
DD
level can be at 3 V, or vice versa. A
typical split supply configuration is shown in Figure 73.
Rev. A | Page 83 of 92
0
ADuC7026
0.1
μ
F
ANALOG
SUPPLY
10
μ
F
73
74
AV
DD
75
DACV
DD
8
GND
REF
DACGND
70
71
AGND
67
REFGND
26
IOV
DD
54
25
IOGND
53
0.1
μ
F
+
DIGITAL
SUPPLY
10
μ
F
+
Figure 73. External Dual Supply Connections
As an alternative to providing two separate power supplies, the
user can reduce noise on AV
DD
by placing a small series resistor
and/or ferrite bead between AV
DD
and IOV
DD
, and then
decouple AV
DD
separately to ground. An example of this
configuration is shown in Figure 74. With this configuration,
other analog circuitry (such as op amps, voltage reference, and
others) can be powered from the AV
DD
supply line as well.
0
ADuC7026
0.1
μ
F
BEAD
1.6
Ω
73
74
AV
DD
75
DACV
DD
8
GND
REF
DACGND
70
71
AGND
67
REFGND
26
IOV
DD
54
25
IOGND
53
0.1
μ
F
DIGITAL SUPPLY
10
μ
F
10
μ
F
+
Figure 74. External Single Supply Connections
Notice that in both Figure 73 and Figure 74, a large value
(10
μ
F) reservoir capacitor sits on IOV
DD
, and a separate 10
μ
F
capacitor sits on AV
DD
. In addition, local small-value (0.1
μ
F)
capacitors are located at each AV
DD
and IOV
DD
pin of the chip.
As per standard design practice, be sure to include all of these
capacitors and ensure the smaller capacitors are close to each
AV
DD
pin with trace lengths as short as possible. Connect the
ground terminal of each of these capacitors directly to the
underlying ground plane. Finally, note that the analog and
digital ground pins on the ADuC7019/7020/7021/7022/
7024/7025/7026/7027 must be referenced to the same system
ground reference point at all times.
Linear Voltage Regulator
Each ADuC7019/7020/7021/7022/7024/7025/7026/7027
requires a single 3.3 V supply, but the core logic requires a 2.6 V
supply. An on-chip linear regulator generates the 2.6 V from
IOV
DD
for the core logic. LV
DD
Pin 21 is the 2.6 V supply for the
core logic. An external compensation capacitor of 0.47
μ
F must
be connected between LV
DD
and DGND (as close as possible to
these pins) to act as a tank of charge as shown Figure 75.
0
ADuC7026
0.47
μ
F
27
LV
DD
28
DGND
Figure 75. Voltage Regulator Connections
The LV
DD
pin should not be used for any other chip. It is also
recommended to use excellent power supply decoupling on
IOV
DD
to help improve line regulation performance of the on-
chip voltage regulator.
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