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參數資料
| 型號： | ADUuC7027BSTZ62-RL |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU |
| 中文描述： | 精密模擬微控制器的12位模擬I / O，ARM7TDMI的微控制器 |
| 文件頁數： | 62/92頁 |
| 文件大小： | 850K |
| 代理商： | ADUUC7027BSTZ62-RL |
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ADuC7019/20/21/22/24/25/26/27
SERIAL PORT MUX
The serial port mux multiplexes the serial port peripherals
(an SPI, UART, and two I
2
Cs) and the programmable logic array
(PLA) to a set of ten GPIO pins. Each pin must be configured to
one of its specific I/O functions as described in Table 45.
Table 45. SPM Configuration
GPIO
UART
Pin
(00)
(01)
SPM0
P1.0
SIN
SPM1
P1.1
SOUT
SPM2
P1.2
RTS
SPM3
P1.3
CTS
SPM4
P1.4
RI
SPM5
P1.5
DCD
SPM6
P1.6
DSR
SPM7
P1.7
DTR
SPM8
P0.7
ECLK/XCLK
SPM9
P2.0
CONV
Rev. A | Page 62 of 92
UART/I
2
C/SPI
(10)
I2C0SCL
I2C0SDA
I2C1SCL
I2C1SDA
SPICLK
SPIMISO
SPIMOSI
SPICSL
SIN
SOUT
PLA
(11)
PLAI[0]
PLAI[1]
PLAI[2]
PLAI[3]
PLAI[4]
PLAI[5]
PLAI[6]
PLAO[0]
PLAO[4]
PLAO[5]
Table 45 also details the mode for each of the SPMUX GPIO
pins. This configuration has to be done via the GP0CON,
GP1CON, and GP2CON MMRs. By default these ten pins are
configured as GPIOs.
UART SERIAL INTERFACE
The UART peripheral is a full-duplex, universal, asynchronous
receiver/transmitter. It is fully compatible with the 16450 serial port
standard. The UART performs serial-to-parallel conversion on data
characters received from a peripheral device or modem, and
parallel-to-serial conversion on data characters received from the
CPU. The UART includes a fractional divider for baud rate
generation and has a network addressable mode. The UART
function is made available on the 10 pins of the ADuC7019/7020/
7021/7022/7024/7025/7026/7027 (see Table 46).
Table 46. UART Signal Description
Pin
Signal
SPM0 (Mode 1)
SIN
SPM1 (Mode 1)
SOUT
SPM2 (Mode 1)
RTS
SPM3 (Mode 1)
CTS
SPM4 (Mode 1)
RI
SPM5 (Mode 1)
DCD
SPM6 (Mode 1)
DSR
SPM7 (Mode 1)
DTR
SPM8 (Mode 2)
SIN
SPM9 (Mode 2)
SOUT
Description
Serial Receive Data
Serial Transmit Data
Request to Send
Clear to Send
Ring Indicator
Data Carrier Detect
Data Set Ready
Data Terminal Ready
Serial Receive Data
Serial Transmit Data
The serial communication adopts an asynchronous protocol,
which supports various word lengths, stop bits, and parity
generation options selectable in the configuration register.
Baud Rate Generation
There are two ways of generating the UART baud rate.
1.
Normal 450 UART Baud Rate Generation.
The baud rate is a divided version of the core clock using the
value in COMDIV0 and COMDIV1 MMRs (16-bit value, DL).
DL
rate
Baud
CD
×
×
×
=
2
16
2
MHz
78
.
41
Table 47 gives some common baud rate values.
Table 47. Baud Rate Using the Normal Baud Rate Generator
Baud Rate
CD
DL
Actual Baud Rate
9600
0
88 h
9600
19200
0
44 h
19200
115200
0
0B h
118691
9600
3
11 h
9600
19200
3
8 h
20400
115200
3
1 h
163200
% Error
0
0
3
0
6.25
41.67
2.
Using the Fractional Divider.
The fractional divider combined with the normal baud rate
generator produces a wider range of more accurate baud rates.
0
/16DL
UART
FBEN
CORE
CLOCK
/2
/(M+N/2048)
Figure 61. Baud Rate Generation Options
Calculation of the baud rate using fractional divider is as
follows:
)
(
2048
2
16
2
MHz
78
.
41
N
M
DL
Rate
Baud
CD
+
×
×
×
×
=
2
16
2
MHz
×
78
.
×
41
2048
×
×
=
+
DL
Rate
Baud
N
M
CD
For example, generation of 19,200 baud with CD bits = 3
(Table 47 gives DL = 8 h),
2
8
16
2
19200
MHz
×
78
3
.
41
2048
×
×
×
=
+
N
M
06
.
2048
=
+
N
M
where:
M
= 1
N
= 0.06 × 2048 = 128
×
×
×
×
=
2048
128
2
8
16
2
MHz
78
.
41
3
Rate
Baud
where:
Baud Rate
= 19,200 bps
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