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參數資料
| 型號： | ADUuC7027BSTZ62-RL |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU |
| 中文描述： | 精密模擬微控制器的12位模擬I / O，ARM7TDMI的微控制器 |
| 文件頁數： | 54/92頁 |
| 文件大小： | 850K |
| 代理商： | ADUUC7027BSTZ62-RL |
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ADuC7019/20/21/22/24/25/26/27
40-Pin Package Devices
On the 40-pin package devices, the PWM outputs are not
directly accessible, as described in the General-Purpose
Input/Output section. One channel can be brought out on a
GPIO via the PLA as shown in this example:
Rev. A | Page 54 of 92
PWMCON = 0x1;
PWMDAT0 = 0x055F;
// enables PWM o/p
// PWM switching freq
// Configure Port Pins
GP4CON = 0x300;
GP3CON = 0x1;
// P4.2 as PLA output
// P3.0 configured as
// output of PWM0
//(internally)
// PWM0 onto P4.2
PLAELM8 = 0x0035;
PLAELM10 = 0x0059; // PWM from element 8
// P3.0 (PWM output)
// input of element 8
Description of the PWM Block
A functional block diagram of the PWM controller is shown in
Figure 56. The generation of the six output PWM signals on
pins PWM0
H
to PWM2
L
is controlled by four important blocks:
The Three-Phase PWM Timing Unit. The core of the PWM
controller, it generates three pairs of complemented and dead-
time-adjusted, center-based PWM signals.
The Output Control Unit. This block can redirect the
outputs of the three-phase timing unit for each channel to
either the high-side or low-side output. In addition, the
output control unit allows individual enabling/disabling of
each of the six PWM output signals.
The Gate Drive Unit. This block can generate the high
frequency chopping frequency and its subsequent mixing
with the PWM signals.
The PWM Shutdown Controller. This block takes care of
the PWM shutdown via the PWM
TRIP
pin and generates the
correct reset signal for the timing unit.
The PWMSYNC pulse control unit generates the internal
synchronization pulse and also controls whether the external
PWM
SYNC
pin is used or not.
The PWM controller is driven by the ADuC7019/7020/
7021/7022/7024/7025/7026/7027 core clock frequency and is
capable of generating two interrupts to the ARM core. One
interrupt is generated on the occurrence of a PWMSYNC pulse,
and the other is generated on the occurrence of any PWM
shutdown action.
0
PWM0
H
PWM0
L
PWM1
H
PWM1
L
PWM2
H
PWM2
L
PWMCON
PWMDAT0
PWMDAT1
PWMDAT2
PWMCH0
PWMCH1
PWMCH2
CONFIGURATION
REGISTERSDUTY CYCLE
REGISTERS
THREE-PHASE
PWM TIMING
UNIT
PWMEN
OUTPUT
CONTROL
UNIT
PWM
SHUTDOWN
CONTROLLER
PWMCFG
GATE
DRIVE
UNIT
PWM
SYNC
PWM
TRIP
TO INTERRUPT
CONTROLLER
SYNC
CORE CLOCK
Figure 56. Overview of the PWM Controller
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