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參數資料
型號: ADUuC7027BSTZ62-RL
廠商: Analog Devices, Inc.
英文描述: Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU
中文描述: 精密模擬微控制器的12位模擬I / O,ARM7TDMI的微控制器
文件頁數: 79/92頁
文件大小: 850K
代理商: ADUUC7027BSTZ62-RL
ADuC7019/20/21/22/24/25/26/27
Table 77. T3CON MMR Bit Descriptions
Bit
Value
Description
31:9
Reserved.
8
Count Up.
Set
by user for Timer3 to count up.
Cleared
by user for Timer3 to count down by
default.
7
Timer3 Enable Bit.
Set
by user to enable
Timer3.
Cleared
by user to disable Timer3 by
default.
6
Timer3 Mode.
Set
by user to operate in
periodic mode.
Cleared
by user to operate
in free-running mode. Default mode.
5
Watchdog Mode Enable Bit.
Set
by user to
enable watchdog mode.
Cleared
by user to
disable watchdog mode by default.
4
Secure Clear Bit.
Set
by user to use the secure
clear option.
Cleared
by user to disable the
secure clear option by default.
3:2
Prescale:
00
Source Clock/1 by Default.
01
Source Clock/16.
10
Source Clock/256.
11
Undefined. Equivalent to 00.
1
Watchdog IRQ Option Bit.
Set
by user to
produce an IRQ instead of a reset when
the watchdog reaches 0.
Cleared
by user to
disable the IRQ option.
0
Reserved.
T3CLRI Register
Name
Address
T3CLRI
0xFFFF036C
Rev. A | Page 79 of 92
Default Value
0x00
Access
W
T3CLRI is an 8-bit register. Writing any value to this register
clears the Timer3 interrupt in normal mode or resets a new
timeout period in watchdog mode.
Secure Clear Bit (Watchdog Mode Only)
The secure clear bit is provided for a higher level of protection.
When set, a specific sequential value must be written to T3ICLR
to avoid a watchdog reset. The value is a sequence generated by
the 8-bit linear feedback shift register (LFSR) polynomial = X8
+ X6 + X5 + X + 1 as shown in Figure 67.
0
CLOCK
Q
D
4
Q
D
5
Q
D
3
Q
D
7
Q
D
6
Q
D
2
Q
D
1
Q
D
0
Figure 67. 8-Bit LFSR
The initial value or seed is written to T3ICLR before entering
watchdog mode. After entering watchdog mode, a write to
T3ICLR must match this expected value. If it matches, the
LFSR is advanced to the next state when the counter reload
happens. If it fails to match the expected state, reset is
immediately generated, even if the count has not yet expired.
The value 0×00 should not be used as an initial seed due to the
properties of the polynomial. The value 0×00 is always
guaranteed to force an immediate reset. The value of the LFSR
cannot be read; it must be tracked/generated in software.
Example of a sequence:
1.
Enter initial seed, 0×AA, in T3ICLR before starting Timer3
in watchdog mode.
Enter 0×AA in T3ICLR; Timer3 is reloaded.
Enter 0×37 in T3ICLR; Timer3 is reloaded.
Enter 0×6E in T3ICLR; Timer3 is reloaded.
Enter 0×66. 0×DC was expected; the watchdog reset the chip.
2.
3.
4.
5.
EXTERNAL MEMORY INTERFACING
The ADuC7026 and ADuC7027 are the only models in their
series that feature an external memory interface The external
memory interface requires a larger number of pins. This is why
it is only available on larger pin count packages. The XMCFG
MMR must be set to 1 to use the external port.
Although 32-bit addresses are supported internally, only the
lower 16 bits of the address are on external pins.
The memory interface can address up to four 128 kB of
asynchronous memory (SRAM or/and EEPROM).
The pins required for interfacing to an external memory are
shown in Table 78.
Table 78. External Memory Interfacing Pins
Pin
Function
AD[15:0]
Address/Data Bus
A16
Extended Addressing for 8-Bit Memory Only
MS[3:0]
Memory Select Pins
WR
Write Strobe
RS
Read Strobe
AE
Address Latch Enable
BHE, BLE
Byte Write Capability
There are four external memory regions available as described
in Table 79. Associated with each region are the pins MS[3:0].
These signals allow access to the particular region of external
memory. The size of each memory region can be 128 kB maxi-
mum, 64 k × 16 or 128 k × 8. To access 128 k with an 8-bit
memory, an extra address line (A16) is provided. (See the
example in Figure 68.) The four regions are configured
independently.
Table 79. Memory Regions
Address Start
Address End
0x10000000
0x1000FFFF
0x20000000
0x2000FFFF
0x30000000
0x3000FFFF
0x40000000
0x4000FFFF
Contents
External Memory 0
External Memory 1
External Memory 2
External Memory 3
Each external memory region can be controlled through three
MMRs: XMCFG, XMxCON, and XMxPAR.
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