
ADV7180
Rev. A | Page 100 of 112
User Sub Map
Address Register
0x4A
Bit
(Shading Indicates
Default State)
7 6 5 4 3 2 1 0
Comments
No change in SD signal standard
detected at the output
A change in SD signal standard is
detected at the output
No change in SD vsync lock status
SD vsync lock status has changed
No change in SD hsync lock status
SD hsync lock status has changed
No change in AD_RESULT[2:0] bits in
Status Register 1
AD_RESULT[2:0] bits in Status Register 1
have changed
No change in SECAM lock status
SECAM lock status has changed
No change in PAL swinging burst
lock status
PAL swinging burst lock status has
changed
Not used
Not used
Do not clear
Clears SD_OP_CHNG_Q bit
Do not clear
Clears SD_V_LOCK_CHNG_Q bit
Do not clear
Clears SD_H_LOCK_CHNG_Q bit
Do not clear
Clears SD_AD_CHNG_Q bit
Do not clear
Clears SCM_LOCK_CHNG_Q bit
Do not clear
Clears PAL_SW_LK_CHNG_Q bit
Not used
Not used
Masks SD_OP_CHNG_Q bit
Unmasks SD_OP_CHNG_Q bit
Masks SD_V_LOCK_CHNG_Q bit
Unmasks SD_V_LOCK_CHNG_Q bit
Masks SD_H_LOCK_CHNG_Q bit
Unmasks SD_H_LOCK_CHNG_Q bit
Masks SD_AD_CHNG_Q bit
Unmasks SD_AD_CHNG_Q bit
Masks SCM_LOCK_CHNG_Q bit
Unmasks SCM_LOCK_CHNG_Q bit
Masks PAL_SW_LK_CHNG_Q bit
Unmasks PAL_SW_LK_CHNG_Q bit
Not used
Not used
Bit Description
SD_OP_CHNG_Q. SD 60 Hz/50 Hz
frame rate at output.
Notes
These bits can be cleared
and masked by Registers
0x4B and 0x4C,
respectively
0
1
0
0
1
0
1
SD_V_LOCK_CHNG_Q.
SD_H_LOCK_CHNG_Q.
SD_AD_CHNG_Q. SD autodetect
changed.
1
0
0
1
SCM_LOCK_CHNG_Q. SECAM lock.
PAL_SW_LK_CHNG_Q.
1
Reserved.
Reserved.
SD_OP_CHNG_CLR.
x
x
x
x
x
x
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Interrupt Status 3
(Read Only)
SD_V_LOCK_CHNG_CLR.
0
1
SD_H_LOCK_CHNG_CLR.
0
1
SD_AD_CHNG_CLR.
0
1
SCM_LOCK_CHNG_CLR.
0
1
PAL_SW_LK_CHNG_CLR.
Reserved.
Reserved.
SD_OP_CHNG_MSK.
0
1
0x4B
Interrupt Clear 3
(Write only)
SD_V_LOCK_CHNG_ MSK.
SD_H_LOCK_CHNG_ MSK.
SD_AD_CHNG_ MSK.
SCM_LOCK_CHNG_ MSK.
PAL_SW_LK_CHNG_ MSK.
Reserved.
Reserved.
0x4C
Interrupt Mask 3
(Read/Write)