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參數資料
型號: ADV7180
廠商: Analog Devices, Inc.
英文描述: 10-Bit, 4 x Oversampling SDTV Video Decoder
中文描述: 10位,4個采樣標清視頻解碼器
文件頁數: 16/112頁
文件大小: 1320K
代理商: ADV7180
ADV7180
INPUT CONFIGURATION
There are two key steps for configuring the ADV7180 to
correctly decode the input video.
1.
Use INSEL[3:0] to configure routing and format decoding
(CVBS, Y/C, or YPrPb). For the ADV7180 LQFP-64, see
Table 10. For ADV7180 LFCSP-40, see Table 11.
2.
If the input requirements are not met using the INSEL[3:0]
options, the analog input muxing section must be
configured manually to correctly route the video from the
analog input pins to the ADC. The standard definition
processor block, which decodes the digital data, should be
configured to process either CVBS, Y/C, or YPrPb format.
This is performed by INSEL[3:0] selection.
Rev. A | Page 16 of 112
CONNECT ANALOG VIDEO
SIGNALS TO ADV7180.
SET INSEL[3:0] TO CONFIGURE
VIDEO FORMAT. USE PREDEFINED
FORMAT/ROUTING.
CONFIGURE ADC INPUTS USING
MANUAL MUXING CONTROL BITS:
MUX_0[3:0], MUX_1[3:0], MUX_2[3:0].
SEE TABLE 12.
REFER TO
TABLE 10
REFER TO
TABLE 11
LQFP-64
LFCSP-40
0
NO
YES
Figure 11. Signal Routing Options
INSEL[3:0], INPUT SELECTION, ADDRESS 0x00
[3:0]
The INSEL bits allow the user to select the input format. They
also configure the standard definition processor core to process
composite (CVBS), S-video (Y/C), or component (YPrPb)
format.
INSEL[3:0] has predefined analog input routing schemes that
do not require manual mux programming (see Table 10 and
Table 11). This allows the user to route the various video signal
types to the decoder and select them using INSEL[3:0] only.
The added benefit is that if, for example, CVBS input is selected,
the remaining channels are powered down.
Table 10. ADV7180 LQFP-64 INSEL[3:0]
INSEL[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011 to 1111
Video Format
Composite
Composite
Composite
Composite
Composite
Composite
Y/C (S-video)
Y/C (S-video)
Y/C (S-video)
YPrPb
YPrPb
Not used
Analog Input
CVBS
A
IN
1
CVBS
A
IN
2
CVBS
A
IN
3
CVBS
A
IN
4
CVBS
A
IN
5
CVBS
A
IN
6
Y
A
IN
1
C
A
IN
4
Y
A
IN
2
C
A
IN
5
Y
A
IN
3
C
A
IN
6
Y
A
IN
1
Pb
A
IN
4
Pr
A
IN
5
Y
A
IN
2
Pr
A
IN
6
Pb
A
IN
3
Not used
Table 11. ADV7180 LFCSP-40 INSEL[3:0]
INSEL[3:0]
0000
0001 to 0010
0011
0100
0101
0110
0111 to 1000
1001
1010 to 1111
Video Format
Composite
Not used
Composite
Composite
Not used
Y/C (S-video)
Analog Input
CVBS
A
IN
1
Not used
CVBS
A
IN
2
CVBS
A
IN
3
Not used
Y
A
IN
1
C
A
IN
2
Not used
Y
A
IN
1
Pr
A
IN
3
Pb
A
IN
2
Not used
Not used
YPrPb
Not used
相關PDF資料
PDF描述
ADV7180BCPZ 10-Bit, 4 x Oversampling SDTV Video Decoder
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