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參數資料
| 型號： | ADV7180 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 10-Bit, 4 x Oversampling SDTV Video Decoder |
| 中文描述： | 10位，4個采樣標清視頻解碼器 |
| 文件頁數： | 49/112頁 |
| 文件大小： | 1320K |
| 代理商： | ADV7180 |
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ADV7180
Rev. A | Page 49 of 112
ADVANCE END OF
VSYNC BY PVEND[4:0]
DELAY END OF VSYNC
BY PVEND[4:0]
VSYNC END
PVENDSIGN
ODD FIELD
0
1
NO
YES
PVENDDELO
VSEHO
ADDITIONAL
DELAY BY
1 LINE
ADVANCE BY
0.5 LINE
1
0
1
0
PVENDDELE
VSEHE
ADDITIONAL
DELAY BY
1 LINE
ADVANCE BY
0.5 LINE
1
0
1
0
NOT VALID FOR USER
PROGRAMMING
0
PFTOGDELO, PAL Field Toggle Delay on Odd Field,
Address 0xEA [7]
When PFTOGDELO is 0 (default), there is no delay.
Setting PFTOGDELO to 1 delays the F toggle/transition on an
odd field by a line relative to PFTOG.
PFTOGDELE, PAL Field Toggle Delay on Even Field,
Address 0xEA [6]
When PFTOGDELE is 0, there is no delay.
Setting PFTOGDELE to 1 (default) delays the F toggle/transition
on an even field by a line relative to PFTOG.
PFTOGSIGN, PAL Field Toggle Sign, Address 0xEA [5]
Setting PFTOGSIGN to 0 delays the field transition. Set for user
manual programming.
Setting PFTOGSIGN to 1 (default) advances the field transition.
Not recommended for user programming.
PFTOG, PAL Field Toggle, Address 0xEA [4:0]
The default value of PFTOG is 00011, indicating the PAL field
toggle position.
For all NTSC/PAL field timing controls, the F bit in the AV
code and the field signal on the FIELD/DE pin are modified.
ADVANCE TOGGLE OF
FIELD BY PFTOG[4:0]
DELAY TOGGLE OF
FIELD BY PFTOG[4:0]
PFTOGSIGN
ODD FIELD
0
1
NO
YES
PFTOGDELE
ADDITIONAL
DELAY BY
1 LINE
1
0
PFTOGDELO
ADDITIONAL
DELAY BY
1 LINE
1
0
FIELD
TOGGLE
NOPROGRAMMING
0
Figure 41. PAL Vsync End
PVENDDELO, PAL Vsync End Delay on Odd Field,
Address 0xE9 [7]
When PVENDDELO is 0 (default), there is no delay.
Setting PVENDDELO to 1 delays vsync going low on an odd
field by a line relative to PVEND.
PVENDDELE, PAL Vsync End Delay on Even Field,
Address 0xE9 [6]
When PVENDDELE is 0 (default), there is no delay.
Setting PVENDDELE to 1 delays vsync going low on an even
field by a line relative to PVEND.
PVENDSIGN, PAL Vsync End Sign, Address 0xE9 [5]
Setting PVENDSIGN to 0 (default) delays the end of vsync. Set
for user manual programming.
Setting PVENDSIGN to 1 advances the end of vsync. Not
recommended for user programming.
PVEND[4:0], PAL Vsync End, Address 0xE9 [4:0]
The default value of PVEND is 10100, indicating the PAL vsync
end position.
For all NTSC/PAL vsync timing controls, both the V bit in the
AV code and the vsync on the VS pin are modified.
Figure 42. PAL F Toggle
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PDF描述 |
|---|---|
| ADV7180BCPZ | 10-Bit, 4 x Oversampling SDTV Video Decoder |
| ADV7180BSTZ | 10-Bit, 4 x Oversampling SDTV Video Decoder |
| ADV7181 | Multiformat SDTV Video Decoder |
| ADV7181B | Multiformat SDTV Video Decoder |
| ADV7181BBCPZ | Multiformat SDTV Video Decoder |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ADV7180_12 | 制造商:AD 制造商全稱:Analog Devices 功能描述:10-Bit, 4?? Oversampling SDTV Video Decoder |
| ADV7180BCP32Z | 制造商:Analog Devices 功能描述:10-BIT, 4? OVERSAMPLING SDTV VIDEO DECODER - Trays |
| ADV7180BCP32Z-RL | 制造商:Analog Devices 功能描述:IC |
| ADV7180BCPZ | 功能描述:IC VIDEO DECODER SDTV 40-LFCSP RoHS:是 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 標準包裝:250 系列:- 類型:電平移位器 應用:LCD 電視機/監控器 安裝類型:表面貼裝 封裝/外殼:28-WFQFN 裸露焊盤 供應商設備封裝:28-WQFN（4x4）裸露焊盤 包裝:帶卷 (TR) 其它名稱:296-32523-2TPS65198RUYT-ND |
| ADV7180BCPZ | 制造商:Analog Devices 功能描述:IC VIDEO DECODER 10BIT 57.27MSPS LFCSP40 |
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