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參數資料
| 型號： | ISP1761 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Hi-Speed Universal Serial Bus On-The-Go controller |
| 中文描述： | 高速通用串行總線和On - The - Go控制器 |
| 文件頁數： | 17/158頁 |
| 文件大小： | 724K |
| 代理商： | ISP1761 |
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9397 750 13258
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 12 January 2005
17 of 158
Philips Semiconductors
ISP1761
Hi-Speed USB OTG controller
The total amount of memory allocated to the payload determines the maximum transfer
size specified by a PTD—a bigger internal memory size results in less CPU interruption
for transfer programming. This means less time spent in context switching, resulting in
better CPU usage.
A larger buffer also implies a larger amount of data can be transferred. This transfer,
however, can be done over a longer period of time, to maintain the overall system
performance. Each transfer of the USB data on the USB bus can span up to a few
milliseconds before requiring further CPU intervention for data movement.
The internal architecture of the ISP1761 allows a flexible definition of the memory buffer
for optimization of the data transfer on the CPU extension bus and the USB. It is possible
to implement different data transfer schemes, depending on the number and type of USB
devices present (for example: push-pull—data can be written to half of the memory while
data in the other half is being accessed by the Host Controller and sent on the USB bus).
This is useful especially when a high-bandwidth ‘continuous or periodic’ data flow is
required.
Through an analysis of the hardware and software environment regarding the usual data
flow and performance requirements of most embedded systems, Philips has determined
the optimal size for the internal buffer as approximately 64 kB.
7.2.2
Structure of the ISP1761 Host Controller memory
The 63 kB of internal memory consists of the PTD area and the payload area.
Both the PTD and payload memory zones are divided into three dedicated areas for each
main type of USB transfer: isochronous (ISO), interrupt (INT) and Acknowledged Transfer
List (ATL). As shown in
Table 4
, the PTD areas for ISO, INT and ATL are grouped at the
beginning of the memory, occupying the address range 0400h to 0FFFh, following the
address space of the registers. The payload or data area occupies the next memory
address range 1000h to FFFFh, meaning that 60 kB of memory are allocated for the
payload data.
A maximum of 32 PTD areas and their allocated payload areas can be defined for each
type of transfer. The structure of a PTD is similar for every transfer type and consists of
eight Double Words (DWs) that must be correctly programmed for a correct USB data
transfer. The reserved bits of a PTD must be set to logic 0. A detailed description of the
PTD structure can be found in
Section 8.5
.
The transfer size specified by the PTD determines the contiguous USB data transfer that
can be performed without any CPU intervention. The respective payload memory area
must be equal to the transfer size defined. The maximum transfer size is flexible and can
be optimized, depending on the number and nature of USB devices or PTDs defined and
their respective MaxPacketSize.
The CPU will program the DMA to transfer the necessary data in the payload memory.
The next CPU intervention will be required only when the current transfer is completed
and DMA programming is necessary to transfer the next data payload. This is normally
signaled by the IRQ that is generated by the ISP1761 on completing the current PTD,
meaning all the data in the payload area was sent on the USB bus. The external IRQ
signal is asserted according to the settings in the IRQ Mask OR or IRQ MASK AND
registers, see
Section 8.4
.
相關PDF資料 |
PDF描述 |
|---|---|
| ISP1761BE | Hi-Speed Universal Serial Bus On-The-Go controller |
| ISP1761ET | Hi-Speed Universal Serial Bus On-The-Go controller |
| ISP2100A | Telecommunication IC |
| ISP2100BN4 | Microprocessor |
| ISP2300 | Controller Miscellaneous - Datasheet Reference |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ISP1761BE | 功能描述:USB 接口集成電路 USB HS OTG CTRLR RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1761BE,518 | 功能描述:USB 接口集成電路 USB HS OTG CONTROLLER RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1761BE,551 | 功能描述:USB 接口集成電路 DO NOT USE ORDER -T OR NO "-" RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1761BE,557 | 功能描述:USB 接口集成電路 USB HS OTG CTRLR RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1761BE518 | 制造商:ST-Ericsson 功能描述:IC CONTROLLER USB OTG 128LQFP |
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