
9397 750 13258
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 12 January 2005
2 of 158
Philips Semiconductors
ISP1761
Hi-Speed USB OTG controller
I
Separate IRQ, DREQ and DACK lines for the Host Controller and the Peripheral
Controller
I
Integrated multiconfiguration FIFO
I
Double-buffering scheme increases throughput and facilitates real-time data transfer
I
Integrated Phase-Locked Loop (PLL) with external 12 MHz crystal for low EMI
I
Tolerant I/O for low voltage CPU interface (1.65 V to 3.3 V)
I
3.3 V-to-5.0 V external power supply input
I
Integrated 5.0 V-to-1.8 V or 3.3 V-to-1.8 V voltage regulator (internal 1.8 V for
low-power core)
I
Internal power-on reset or low-voltage reset and block-dedicated software reset
I
Supports suspend and remote wake-up
I
Built-in overcurrent circuitry (analog overcurrent protection)
I
Hybrid-power mode: V
CC(5V0)
(can be switched off), V
CC(I/O)
(permanent)
I
Target total current consumption:
N
Normal operation; one port in high-speed active: I
CC
< 100 mA when the internal
charge pump is not used
N
Suspend mode: I
CC(susp)
< 150
μ
A at the room temperature
I
Available in LQFP128 and TFBGA128 packages
I
Host Controller-specific features
N
High performance USB host with integrated high-speed USB transceivers;
supports high-speed, full-speed and low-speed
N
The EHCI core is adapted from Enhanced Host Controller Interface Specification
for Universal Serial Bus Rev. 1.0
N
Configurable power management
N
Integrated TT for Original USB peripheral support on all three ports
N
Integrated 64 kB high-speed memory (internally organized as 8 k X 64 bits)
N
Additional 2.5 kB separate memory for TT
N
Individual or global overcurrent protection with built-in sense circuits
N
Overcurrent circuitry built-in (digital or analog overcurrent protection)
I
OTG Controller-specific features
N
OTG transceiver: fully integrated; compliant with On-The-Go Supplement to the
USB Specification Rev. 1.0a
N
Supports HNP and SRP for OTG dual-role devices
N
HNP: status and control registers for software implementation
N
SRP: status and control registers for software implementation
N
Programmable timers with high resolution (0.01 ms to 80 ms)—for HNP and SRP
N
Supports external source of V
BUS
I
Peripheral Controller-specific features
N
High-performance USB Peripheral Controller with integrated Serial Interface
Engine (SIE), FIFO memory and transceiver
N
Complies with Universal Serial Bus Specification Rev. 2.0and most device class
specifications
N
Supports auto Hi-Speed USB mode discovery and Original USB fallback
capabilities
N
Supports high-speed and full-speed on the Peripheral Controller
N
Bus-powered or self-powered capability with suspend mode