- 您現在的位置：買賣IC網 > PDF目錄360999 > ISP1761 (NXP Semiconductors N.V.) Hi-Speed Universal Serial Bus On-The-Go controller PDF資料下載
參數資料
| 型號： | ISP1761 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Hi-Speed Universal Serial Bus On-The-Go controller |
| 中文描述： | 高速通用串行總線和On - The - Go控制器 |
| 文件頁數： | 20/158頁 |
| 文件大小： | 724K |
| 代理商： | ISP1761 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁當前第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁
9397 750 13258
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 12 January 2005
20 of 158
Philips Semiconductors
ISP1761
Hi-Speed USB OTG controller
register access must always be completed using two subsequent accesses. In the case of
a DMA transfer, the 16-bit or 32-bit data bus width configuration will determine the number
of bursts that will complete a certain transfer length.
In PIO mode, CS_N, WR_N and RD_N are used to access registers and memory. In DMA
mode, the data validation is performed by DACK—instead of CS_N—together with the
WR_N and RD_N signals. The DREQ signal will always be asserted as soon as the
ISP1761 DMA is enabled, as described in the following section.
7.3.1
PIO mode access—memory read cycle
The following method has been implemented to reduce the read access timing in the case
of a memory read:
The Memory register contains the starting address and the bank selection to read
from the memory. Before every new read cycle of the same or different banks, an
appropriate value is written to this register.
Once a value is written to this register, the address is stored in the FIFO of that bank
and is then used to prefetch data for the memory read of that bank.
For every subsequent read operation executed at a contiguous address, the address
pointer corresponding to that bank is automatically incremented to prefetch the next
data to be sent to the CPU.
Memory read accesses for multiple banks can be interleaved. In this case, the FIFO
block handles the MUXing of appropriate data to the CPU.
The address written to the Memory register is incremented and used to successively
prefetch data from the memory irrespective of the value on the address bus for each
bank, until a new value for a bank is written to the Memory register.
For example, consider the following sequence of operations:
–
Write the starting (read) address 4000h and bank1 = 01 to the Memory register.
When RD_N is asserted for three cycles with A[17:16] = 01, the returned data
corresponds to addresses 4000h, 4004h and 4008h.
Remark:
Once 4000h is written to the Memory register for bank1, the bank select
value determines the successive incremental addresses used to fetch the data.
That is, the fetching of data is independent of the address on A[15:0] lines.
–
Write the starting (read) address 4100h and bank2 = 10 to the Memory register.
When RD_N is asserted for four cycles with A[17:16] = 10, the returned data
corresponds to addresses 4100h, 4104h, 4108h and 410Ch.
Consequently, the RD_N assertion with A[17:16] = 01 will return data from 400Ch
because the bank1 read stopped there in the previous cycle. Also, RD_N
assertions with A[17:16] = 10 will now return data from 4110h because the bank2
read stopped there in the previous cycle.
7.3.2
PIO mode access—memory write cycle
The PIO memory write access is similar to a normal memory access. It is not necessary
to set the prefetching address before a write cycle to memory.
The ISP1761 internal write address will not be automatically incremented during
consecutive write accesses, unlike in a series of ISP1761 memory read cycles. The
memory write address must be incremented before every access.
相關PDF資料 |
PDF描述 |
|---|---|
| ISP1761BE | Hi-Speed Universal Serial Bus On-The-Go controller |
| ISP1761ET | Hi-Speed Universal Serial Bus On-The-Go controller |
| ISP2100A | Telecommunication IC |
| ISP2100BN4 | Microprocessor |
| ISP2300 | Controller Miscellaneous - Datasheet Reference |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ISP1761BE | 功能描述:USB 接口集成電路 USB HS OTG CTRLR RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1761BE,518 | 功能描述:USB 接口集成電路 USB HS OTG CONTROLLER RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1761BE,551 | 功能描述:USB 接口集成電路 DO NOT USE ORDER -T OR NO "-" RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1761BE,557 | 功能描述:USB 接口集成電路 USB HS OTG CTRLR RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1761BE518 | 制造商:ST-Ericsson 功能描述:IC CONTROLLER USB OTG 128LQFP |
發布緊急采購，3分鐘左右您將得到回復。