- 您現在的位置：買賣IC網 > PDF目錄360999 > ISP1761 (NXP Semiconductors N.V.) Hi-Speed Universal Serial Bus On-The-Go controller PDF資料下載
參數資料
| 型號： | ISP1761 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Hi-Speed Universal Serial Bus On-The-Go controller |
| 中文描述： | 高速通用串行總線和On - The - Go控制器 |
| 文件頁數： | 58/158頁 |
| 文件大小： | 724K |
| 代理商： | ISP1761 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁當前第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁
9397 750 13258
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 12 January 2005
58 of 158
Philips Semiconductors
ISP1761
Hi-Speed USB OTG controller
EHCI manages schedules in two lists: periodic and asynchronous. The data structures
are designed to provide the maximum flexibility required by USB, minimize memory traffic,
and hardware and software complexity. The ISP1761 controller executes transactions for
devices by using a simple shared-memory schedule. This schedule consists of data
structures organized into three lists:
qISO —
Isochronous transfer
qINTL —
Interrupt transfer
qATL —
Asynchronous transfer; for the control and bulk transfers.
The system software maintains two lists for the Host Controller: periodic and
asynchronous. The root of the periodic schedule—the PERIODICLISTBASE register—is
the physical memory base address of the periodic frame list. The periodic frame list is an
array memory pointer. The objects referenced from the frame list must be valid schedule
data structures. The asynchronous list base is also a common list of queue heads
(endpoints) that are served in a schedule. These endpoint data structures are further
linked to the EHCI transfer descriptor that is the valid schedule (queue PTD).
The Periodic Schedule Enable (ISO_BUF_FULL and INT_BUF_FULL) or Asynchronous
Schedule Enable (ATL_BUF_FULL) bits can enable traversal to these lists. Enabling a list
indicates the presence of valid schedule in the list. The system software starts at these
points, schedules the first transfer inside the shared memory of the ISP1761, and sets up
the ATL, INTL or ITL bit corresponding to the type of transfer scheduled in the shared
memory.
The ISP1761 has a maximum of 32 ISO, 32 INTL and 32 ATL PTDs. These PTDs are
used as channels to transfer data from the shared memory to the USB bus. These
channels are allocated and deallocated on receiving the transfer from the core USB driver.
Multiple transfers are scheduled to the shared memory for various endpoints by traversing
the next link pointer provided by the EHCI data structure, until it reaches the terminate bit
in a microframe. If a schedule is enabled, the Host Controller starts executing from the
ISO schedule, before it goes to the INTL schedule, and then to the ATL schedule.
The EHCI periodic and asynchronous lists are traversed by the software according to the
EHCI traversal rule, and executed only from the asynchronous schedule after it
encounters the end of the periodic schedule. The Host Controller traverses the ISO, INTL
and ATL schedules. It fetches the element and begins traversing the graph of linked
schedule data structures.
The last bit identifies the end of the schedule for each type of transfer, indicating the rest
of the channels are empty. Once a transition is completed, the Host Controller executes
from the next transfer descriptor in the schedule until the end of the microframe.
The completion of a transfer is indicated to the software by the interrupt that can be
grouped over the various PTDs by using the AND or OR registers that are available for
each schedule type (ISO, INTL and ATL). These registers are simple logic registers to
decide the group and individual PTDs that can interrupt the CPU for a schedule, when the
logical conditions of the done bit is true in the shared memory that completes the interrupt.
Interrupts are of four types and the latency can be programmed in multiples of
μ
SOF
(125
μ
s):
相關PDF資料 |
PDF描述 |
|---|---|
| ISP1761BE | Hi-Speed Universal Serial Bus On-The-Go controller |
| ISP1761ET | Hi-Speed Universal Serial Bus On-The-Go controller |
| ISP2100A | Telecommunication IC |
| ISP2100BN4 | Microprocessor |
| ISP2300 | Controller Miscellaneous - Datasheet Reference |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ISP1761BE | 功能描述:USB 接口集成電路 USB HS OTG CTRLR RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1761BE,518 | 功能描述:USB 接口集成電路 USB HS OTG CONTROLLER RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1761BE,551 | 功能描述:USB 接口集成電路 DO NOT USE ORDER -T OR NO "-" RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1761BE,557 | 功能描述:USB 接口集成電路 USB HS OTG CTRLR RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1761BE518 | 制造商:ST-Ericsson 功能描述:IC CONTROLLER USB OTG 128LQFP |
發布緊急采購，3分鐘左右您將得到回復。