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參數資料
| 型號： | MPC9772 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 3.3V 1:12 LVCMOS PLL Clock Generator |
| 中文描述： | 3.3 1:12的LVCMOS PLL時鐘發生器 |
| 文件頁數： | 13/16頁 |
| 文件大?。?/td> | 238K |
| 代理商： | MPC9772 |
MPC9772
TIMING SOLUTIONS
13
MOTOROLA
The waveform plots in Figure 13. “Single versus Dual Line
Termination Waveforms” show the simulation results of an
output driving a single line versus two lines. In both cases the
drive capability of the MPC9772 output buffer is more than
sufficient to drive 50
transmission lines on the incident edge.
Note from the delay measurements in the simulations a delta of
only 43ps exists between the two differently loaded outputs.
This suggests that the dual line driving need not be used
exclusively to maintain the tight output-to-output skew of the
MPC9772. The output waveform in Figure 13. “Single versus
Dual Line Termination Waveforms” shows a step in the
waveform, this step is caused by the impedance mismatch seen
looking into the driver. The parallel combination of the 36
series resistor plus the output impedance does not match the
parallel combination of the line impedances. The voltage wave
launched down the two lines will equal:
V
L
= V
S
(Z
0
÷
(R
S
+R
0
+Z
0
))
Z
0
= 50
|| 50
R
S
= 36
|| 36
R
0
= 14
V
L
= 3.0 ( 25
÷
(18+17+25)
= 1.31V
At the load end the voltage will double, due to the near unity
reflection coefficient, to 2.6V. It will then increment towards the
quiescent 3.0V in steps separated by one round trip delay (in
this case 4.0ns).
Since this step is well above the threshold region it will not
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To better
match the impedances when driving multiple lines the situation
in Figure 14. “Optimized Dual Line Termination” should be
used. In this case the series terminating resistors are reduced
such that when the parallel combination is added to the output
buffer impedance the line impedance is perfectly matched.
Figure 12. Single versus Dual Transmission Lines
14
IN
MPC9772
OUTPUT
BUFFER
R
S
= 36
Z
O
= 50
OutA
14
IN
MPC9772
OUTPUT
BUFFER
R
S
= 36
Z
O
= 50
OutB0
R
S
= 36
Z
O
= 50
OutB1
Figure 13. Single versus Dual Waveforms
TIME (ns)
V
3.0
2.5
2.0
1.5
1.0
0.5
0
2
4
6
8
10
12
14
OutB
t
D
= 3.9386
OutA
t
D
= 3.8956
In
Figure 14. Optimized Dual Line Termination
14
MPC9772
OUTPUT
BUFFER
R
S
= 22
Z
O
= 50
R
S
= 22
Z
O
= 50
14
+ 22
|| 22
= 50
|| 50
25
= 25
Figure 15. CCLK MPC9772 AC Test Reference
Pulse
Generator
Z = 50
R
T
= 50
Z
O
= 50
R
T
= 50
Z
O
= 50
MPC9772 DUT
V
TT
V
TT
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相關代理商/技術參數 |
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|---|---|
| MPC9772AE | 功能描述:鎖相環 - PLL 2.5 3.3V 250MHz Clock Generator RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| MPC9772AER2 | 功能描述:時鐘發生器及支持產品 FSL 1-12 LVCMOS PLL Clock Generator, xta RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC9772FA | 功能描述:鎖相環 - PLL 3.3V 240MHz Clock Generator RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| MPC9772FAR2 | 功能描述:時鐘發生器及支持產品 FSL 1-12 LVCMOS PLL Clock Generator, xta RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC9773 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:3.3 V 1:12 LVCMOS PLL Clock Generator |
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