- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄382345 > MPC9772 (Motorola, Inc.) 3.3V 1:12 LVCMOS PLL Clock Generator PDF資料下載
參數(shù)資料
| 型號： | MPC9772 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 3.3V 1:12 LVCMOS PLL Clock Generator |
| 中文描述： | 3.3 1:12的LVCMOS PLL時鐘發(fā)生器 |
| 文件頁數(shù)： | 3/16頁 |
| 文件大小： | 238K |
| 代理商： | MPC9772 |
MPC9772
TIMING SOLUTIONS
3
MOTOROLA
Table 1. Pin Configuration
Pin
I/O
Type
Function
CCLK0
Input
LVCMOS
PLL reference clock
CCLK1
Input
LVCMOS
Alternative PLL reference clock
XTAL_IN, XTAL_OUT
Analog
Crystal oscillator interface
FB_IN
Input
LVCMOS
PLL feedback signal input, connect to an QFB
CCLK_SEL
Input
LVCMOS
LVCMOS clock reference select
REF_SEL
Input
LVCMOS
LVCMOS/PECL reference clock select
VCO_SEL
Input
LVCMOS
VCO operating frequency select
PLL_EN
Input
LVCMOS
PLL enable/PLL bypass mode select
MR/OE
Input
LVCMOS
Output enable/disable (high-impedance tristate) and device reset
FSEL_A[0:1]
Input
LVCMOS
Frequency divider select for bank A outputs
FSEL_B[0:1]
Input
LVCMOS
Frequency divider select for bank B outputs
FSEL_C[0:1]
Input
LVCMOS
Frequency divider select for bank C outputs
FSEL_FB[0:2]
Input
LVCMOS
Frequency divider select for the QFB output
INV_CLK
Input
LVCMOS
Clock phase selection for outputs QC2 and QC3
STOP_CLK
Input
LVCMOS
Clock input for clock stop circuitry
STOP_DATA
Input
LVCMOS
Configuration data input for clock stop circuitry
QA[0-3]
Output
LVCMOS
Clock outputs (Bank A)
QB[0-3]
Output
LVCMOS
Clock outputs (Bank B)
QC[0-3]
Output
LVCMOS
Clock outputs (Bank C)
QFB
Output
LVCMOS
PLL feedback output. Connect to FB_IN.
QSYNC
Output
LVCMOS
Synchronization pulse output
GND
Supply
Ground
Negative power supply
V
CC_PLL
Supply
V
CC
PLL positive power supply (analog power supply). It is recommended to use an external RC
filter for the analog power supply pin V
CC_PLL
. Please see applications section for details.
Positive power supply for I/O and core. All V
CC
pins must be connected to the positive power
supply for correct operation
V
CC
Supply
V
CC
Table 2. Function Table (Configuration Controls)
Control
Default
0
1
REF_SEL
1
Selects CCLKx as the PLL reference clock
Selects the crystal oscillator as the PLL
reference clock
CCLK_SEL
1
Selects CCLK0
Selects VCO
÷
2. The VCO frequency is scaled by a factor of 2 (low VCO
frequency range).
Selects CCLK1
Selects VCO
÷
1. (high VCO frequency range)
VCO_SEL
1
PLL_EN
1
Test mode with the PLL bypassed. The reference clock is substituted for the
internal VCO output. MPC9772 is fully static and no minimum frequency limit
applies. All PLL related AC characteristics are not applicable.
Normal operation mode with PLL enabled.
INV_CLK
1
QC2 and QC3 are in phase with QC0 and QC1
QC2 and QC3 are inverted (180
°
phase shift)
with respect to QC0 and QC1
MR/OE
1
Outputs disabled (high-impedance state) and device is reset. During reset/
output disable the PLL feedback loop is open and the internal VCO is tied to
its lowest frequency. The MPC9772 requires reset after any loss of PLL lock.
Loss of PLL lock may occur when the external feedback path is interrupted.
The length of the reset pulse should be greater than one reference clock
cycle (CCLKx). The device is reset by the internal power-on reset (POR)
circuitry during power-up.
Outputs enabled (active)
VCO_SEL, FSEL_A[0:1], FSEL_B[0:1], FSEL_C[0:1], FSEL_FB[0:2] control the operating PLL frequency range and input/output frequency ratios.
See Table 3 to Table 6 and the applications section for supported frequency ranges and output to input frequency ratios.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MPC9893 | Low Voltage PLL Intelligent Dynamic Clock (IDCS) Switch |
| MPC99J93 | Intelligent Dynamic Clock Switch (IDCS) PLL Clock Driver |
| MPD-425V | 250W DC-DC POWER SUPPLY INPUT RANGE: 40~57VDC |
| MPE-902M | SWITCHING POWER SUPPLY |
| MPF102G | JFET VHF Amplifier |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC9772AE | 功能描述:鎖相環(huán) - PLL 2.5 3.3V 250MHz Clock Generator RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| MPC9772AER2 | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 FSL 1-12 LVCMOS PLL Clock Generator, xta RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC9772FA | 功能描述:鎖相環(huán) - PLL 3.3V 240MHz Clock Generator RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| MPC9772FAR2 | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 FSL 1-12 LVCMOS PLL Clock Generator, xta RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC9773 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:3.3 V 1:12 LVCMOS PLL Clock Generator |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。