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參數資料
| 型號： | MPC9772 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 3.3V 1:12 LVCMOS PLL Clock Generator |
| 中文描述： | 3.3 1:12的LVCMOS PLL時鐘發生器 |
| 文件頁數： | 8/16頁 |
| 文件大?。?/td> | 238K |
| 代理商： | MPC9772 |
MPC9772
MOTOROLA
8
TIMING SOLUTIONS
APPLICATIONS INFORMATION
MPC9772 Configurations
Configuring the MPC9772 amounts to properly configuring
the internal dividers to produce the desired output frequencies.
The output frequency can be represented by this formula:
where f
REF
is the reference frequency of the selected input
clock source (CCLKO, CCLK1 or XTAL interface), M is the PLL
feedback divider and N is a output divider. The PLL feedback
divider is configured by the FSEL_FB[2:0] and the output
dividers are individually configured for each output bank by the
FSEL_A[1:0], FSEL_B[1:0] and FSEL_C[1:0] inputs.
The reference frequency f
REF
and the selection of the
feedback-divider M is limited by the specified VCO frequency
range. f
REF
and M must be configured to match the VCO
frequency range of 200 to 480 MHz (200 to 460 MHz for ind.
temp. range) in order to achieve stable PLL operation:
f
VCO,MIN
≤
(f
REF
VCO_SEL
M)
≤
f
VCO,MAX
The PLL post-divider VCO_SEL is either a divide-by-one or
a divide-by-two and can be used to situate the VCO into the
specified frequency range. This divider is controlled by the
VCO_SEL pin. VCO_SEL effectively extends the usable input
frequency range while it has no effect on the output to reference
frequency ratio.
The output frequency for each bank can be derived from the
VCO frequency and output divider:
f
QA[0:3]
= f
VCO
÷
(VCO_SEL
N
A
)
f
QB[0:3]
= f
VCO
÷
(VCO_SEL
N
B
)
f
QC[0:3]
= f
VCO
÷
(VCO_SEL
N
C
)
Table 11 shows the various PLL feedback and output
dividers and Figure 3 and Figure 4 display example
configurations for the MPC9772:
÷
VCO_SEL
÷
M
÷
N
f
REF
f
OUT
f
OUT
= f
REF
M
÷
N
PLL
Table 11. MPC9772 Divider
Divider
Function
VCO_SEL
Values
M
PLL feedback
FSEL_FB[0:3]
÷
1
4, 6, 8, 10, 12, 16
÷
2
8, 12, 16, 20, 24, 32,
40
N
A
Bank A Output
Divider
FSEL_A[0:1]
÷
1
4, 6, 8, 12
÷
2
8, 12, 16, 24
N
B
Bank B Output
Divider
FSEL_B[0:1]
÷
1
4, 6, 8, 10
÷
2
8, 12, 16, 20
N
C
Bank C Output
Divider
FSEL_C[0:1]
÷
1
2, 4, 6, 8
÷
2
4, 8, 12, 16
Figure 3. Example Configuration
Figure 4. Example Configuration
MPC9772
f
ref
= 33.3 MHz
33.3 MHz
100 MHz
33.3 MHz (Feedback)
200 MHz
CCLK0
CCLK1
CCLK_SEL
VCO_SEL
FB_IN
FSEL_A[1:0]
FSEL_B[1:0]
FSEL_C[1:0]
FSEL_FB[2:0]
QA[3:0]
QB[3:0]
QC[3:0]
QFB
1
11
00
00
101
MPC9772 example configuration (feedback of QFB = 33.3 MHz,
f
VCO
=400 MHz, VCO_SEL=
÷
1, M=12, N
A
=12, N
B
=4, N
C
=2).
Frequency Range T
A
= 0°C to +70°C T
A
= –40°C to +85°C
Input
16.6 – 40 MHz
16.6 – 38.33 MHz
QA Outputs
16.6 – 40 MHz
16.6 – 38.33 MHz
QA Outputs
50 – 120 MHz
50 – 115 MHz
QC Outputs
100 – 240 MHz
100 – 230 MHz
MPC9772
f
ref
= 25 MHz
62.5 MHz
62.5 MHz
25 MHz (Feedback)
125 MHz
CCLK0
CCLK1
CCLK_SEL
VCO_SEL
FB_IN
FSEL_A[1:0]
FSEL_B[1:0]
FSEL_C[1:0]
FSEL_FB[2:0]
QA[3:0]
QB[3:0]
QC[3:0]
QFB
1
00
00
00
011
MPC9772 example configuration (feedback of QFB = 25 MHz,
f
VCO
=250 MHz, VCO_SEL=
÷
1, M=10, N
A
=4, N
B
=4, N
C
=2).
Frequency Range T
A
= 0°C to +70°C T
A
= –40°C to +85°C
Input
20 – 48 MHz
20 – 46 MHz
QA Outputs
50 – 120 MHz
50 – 115 MHz
QA Outputs
50 – 120 MHz
50 – 115 MHz
QC Outputs
100 – 240 MHz
100 – 230 MHz
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| MPC9772AE | 功能描述:鎖相環 - PLL 2.5 3.3V 250MHz Clock Generator RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| MPC9772AER2 | 功能描述:時鐘發生器及支持產品 FSL 1-12 LVCMOS PLL Clock Generator, xta RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC9772FA | 功能描述:鎖相環 - PLL 3.3V 240MHz Clock Generator RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| MPC9772FAR2 | 功能描述:時鐘發生器及支持產品 FSL 1-12 LVCMOS PLL Clock Generator, xta RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC9773 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:3.3 V 1:12 LVCMOS PLL Clock Generator |
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