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參數資料
| 型號： | MPC9772 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 3.3V 1:12 LVCMOS PLL Clock Generator |
| 中文描述： | 3.3 1:12的LVCMOS PLL時鐘發生器 |
| 文件頁數： | 7/16頁 |
| 文件大小： | 238K |
| 代理商： | MPC9772 |
MPC9772
TIMING SOLUTIONS
7
MOTOROLA
t
JIT(
)
I/O Phase Jitter RMS (1
σ
)
12
÷
4 feedback
÷
6 feedback
÷
8 feedback
÷
10 feedback
÷
12 feedback
÷
16 feedback
÷
20 feedback
÷
24 feedback
÷
32 feedback
÷
40 feedback
11
86
13
88
16
19
21
22
27
30
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
(VCO=400 MHz)
BW
PLL closed loop bandwidth
13
÷
4 feedback
÷
6 feedback
÷
8 feedback
÷
10 feedback
÷
12 feedback
÷
16 feedback
÷
20 feedback
÷
24 feedback
÷
32 feedback
÷
40 feedback
1.20 –
3.50
0.70 –
2.50
0.50 –
1.80
0.45 –
1.20
0.30 –
1.00
0.25 –
0.70
0.20 –
0.55
0.17 –
0.40
0.12 –
0.30
0.11 –
0.28
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
t
LOCK
Maximum PLL Lock Time
10
ms
1.
2.
3.
4.
AC characteristics apply for parallel output termination of 50
to V
TT
.
In bypass mode, the MPC9772 divides the input reference clock.
The input reference frequency must match the VCO lock range divided by the total feedback divider ratio: f
REF
= f
VCO
÷
(M
VCO_SEL).
The crystal frequency range must both meet the interface frequency range and VCO lock range divided by the feedback divider ratio:
f
XTAL(min, max)
= f
VCO(min, max)
÷
(M
VCO_SEL) and 10 MHz
≤
f
XTAL
≤
25 MHz.
Calculation of reference duty cycle limits: DC
REF,MIN
= t
PW,MIN
f
REF
100% and DC
REF,MAX
= 100% – DC
REF, MIN
.
The MPC9772 will operate with input rise/fall times up to 3.0 ns, but the A.C. characteristics, specifically t
(
)
, t
PW,MIN
, DC and f
MAX
can only be
guaranteed if t
R
, t
F
are within the specified range.
Static phase offset depends on the reference frequency. t
(
)
[s] = t
(
)
[
°
]
÷
(f
REF
360
°
).
Excluding QSYNC output. See application section for part-to-part skew calculation.
Output duty cycle is DC = (0.5
±
200 ps
f
OUT
)
100%. E.g. the DC range at f
OUT
= 100 MHz is 48%<DC<52%. T = output period.
10. Cycle jitter is valid for all outputs in the same divider configuration. See application section for more details.
11. Period jitter is valid for all outputs in the same divider configuration. See application section for more details.
12. I/O jitter is valid for a VCO frequency of 400 MHz. See application section for I/O jitter vs. VCO frequency.
13. –3 dB point of PLL transfer characteristics.
5.
6.
7.
8.
9.
Table 10. AC Characteristics
(V
CC
= 3.3V ± 5%, T
A
= –40° to +85°C)
1
2
(Continued)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
T
A
= 0°C
to +70°C
T
A
= –40°C
to +85°C
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| MPC9772AE | 功能描述:鎖相環 - PLL 2.5 3.3V 250MHz Clock Generator RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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| MPC9772FAR2 | 功能描述:時鐘發生器及支持產品 FSL 1-12 LVCMOS PLL Clock Generator, xta RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
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