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參數資料
| 型號： | N643GT7MI |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 64 Megabit (4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory |
| 中文描述： | 64兆位（4個M x 16位）的CMOS 1.8伏，只有同時讀/寫，突發模式閃存 |
| 文件頁數： | 14/49頁 |
| 文件大小： | 382K |
| 代理商： | N643GT7MI |
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12
Am29BDS643G
25692A2 May 8, 2006
D A T A S H E E T
read access when the device is in either of these
standby modes, before it is ready to read data.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
I
CC3
in the DC Characteristics table represents the
standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device en-
ergy consumption. The device automatically enters
this mode when addresses remain stable for t
ACC
+
60 ns. The automatic sleep mode is independent of
the CE#, WE#, and OE# control signals. Standard ad-
dress access timings provide new data when
addresses are changed. While in sleep mode, output
data is latched and always available to the system.
I
CC4
in the DC Characteristics table represents the
automatic sleep mode current specification.
RESET#: Hardware Reset Input
The RESET# input provides a hardware method of re-
setting the device to reading array data. When
RESET# is driven low for at least a period of t
RP
, the
device immediately terminates any operation in
progress, tristates all outputs, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was
interrupted should be reinitiated once the device is
ready to accept another command sequence, to en-
sure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
SS
±0.2 V, the device
draws CMOS standby current (I
CC4
). If RESET# is
held at V
IL
but not within V
SS
±0.2 V, the standby cur-
rent will be greater.
RESET# may be tied to the system reset circuitry. A
system reset would thus also reset the Flash memory,
enabling the system to read the boot-up firmware from
the Flash memory.
If RESET# is asserted during a program or erase op-
eration, the device requires a time of t
READY
(during
Embedded Algorithms) before the device is ready to
read data again. If RESET# is asserted when a pro-
gram or erase operation is not executing, the reset
operation is completed within a time of t
READY
(not
during Embedded Algorithms). The system can read
data t
RH
after RESET# returns to V
IH
.
Refer to the AC Characteristics tables for RESET# pa-
rameters and to Figure 12 for the timing diagram.
Output Disable Mode
When the OE# input is at V
IH
, output from the device is
disabled. The outputs are placed in the high
impedance state.
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to Table 10 for com-
mand definitions).
The device offers three types of data protection at the
sector level:
■
The sector lock/unlock command sequence dis-
ables or re-enables both program and erase opera-
tions in any sector.
■
When WP# is at V
IL
,
the two outermost sectors are
locked.
■
When V
PP
is at V
IL
, all sectors are locked.
The following hardware data protection measures pre-
vent accidental erasure or programming, which might
otherwise be caused by spurious system level signals
during V
CC
power-up and power-down transitions, or
from system noise.
Low V
CC
Write Inhibit
When V
CC
is less than V
LKO
, the device does not ac-
cept any write cycles. This protects data during V
CC
power-up and power-down. The command register
and all internal program/erase circuits are disabled,
and the device resets to reading array data. Subse-
quent writes are ignored until V
CC
is greater than
V
LKO
. The system must provide the proper signals to
the control inputs to prevent unintentional writes when
V
CC
is greater than V
LKO
.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE#
or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
V
IL
, CE# = V
IH
or WE# = V
IH
. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
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