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參數資料
| 型號： | RM7000-250S |
| 廠商： | PMC-Sierra, Inc. |
| 英文描述： | RM7000⑩ Microprocessor with On-Chip Secondary Cache Datasheet Released |
| 中文描述： | RM7000⑩微處理器與片上二級高速緩存數據發布 |
| 文件頁數： | 14/54頁 |
| 文件大小： | 901K |
| 代理商： | RM7000-250S |
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Proprietary and Confidential to PMC-Sierra, Inc and for its Customer
’
s Internal Use
Document ID: PMC-2002175, Issue 1
14
RM7000
Microprocessor with On-Chip Secondary Cache Datasheet
Released
Figure 4 Pipeline
Note that instruction dependencies, resource conflicts, and branches result in some of the
instruction slots being occupied by
NOP
s.
Integer Unit
4.4
Like the RM5200 Fcamily, the RM7000 implements the MIPS IV Instruction Set Architecture,
and is therefore fully upward compatible with applications that run on processors such as the
R4650 and R4700 that implement the earlier generation MIPS III Instruction Set Architecture.
Additionally, the RM7000 includes two implementation specific instructions not found in the
baseline MIPS IV ISA, but that are useful in the embedded market place. Described in detail in a
later section, these instructions are integer multiply-accumulate and three-operand integer
multiply.
The RM7000 integer unit includes thirty-two general purpose 64-bit registers, the HI/LO result
registers for the two-operand integer multiply/divide operations, and the program counter, or PC.
There are two separate execution units, one of which can execute function, or F, type instructions
and one which can execute memory, or M, type instructions. See above for a description of the
instruction types and the issue rules. As a special case, integer multiply/divide instructions as well
as their corresponding
MFHI
and
MFLO
instructions can only be executed in the F type
execution unit. Within each execution unit the operational characteristics are the same as on
previous MIPS designs with single cycle ALU operations (add, sub, logical, shift), one cycle load
delay, and an autonomous multiply/divide unit.
Register File
The RM7000 has thirty-two general purpose registers with register location 0 (r0) hard wired to a
zero value. These registers are used for scalar integer operations and address calculation. In order
to service the two integer execution units, the register file has four read ports and two write ports
and is fully bypassed both within and between the two execution units to minimize operation
latency in the pipeline.
I0
I1
I2
I3
I4
I5
I6
I7
I8
I9
2I
2I
1I
1I
1R
1R
2R
2R
1A
1A
2A
2A
1D
1D
2D
2D
1W
1W
2W
2W
2I
2I
1I
1I
1R
1R
2R
2R
1A
1A
2A
2A
1D
1D
2D
2D
1W
1W
2W
2W
2I
2I
1I
1I
1R
1R
2R
2R
1A
1A
2A
2A
1D
1D
2D
2D
1W
1W
2W
2W
2I
2I
1I
1I
1R
1R
2R
2R
1A
1A
2A
2A
1D
1D
2D
2D
1W
1W
2W
2W
2I
2I
1I
1I
1R
1R
2R
2R
1A
1A
2A
2A
1D
1D
2D
2D
1W
1W
2W
2W
one cycle
1I-1R:
2I:
2R:
1A:
1A:
2A-2A:
1A-2A:
1D:
2W:
Instruction cache access
Instruction virtual to physical address translation
Register file read, Bypass calculation, Instruction decode, Branch address calculation
Issue or slip decision, Branch decision
Data virtual address calculation
Integer add, logical, shift
Store Align
Data cache access and load align
Data virtual to physical address translation
Register file write
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