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| 型號： | RM7000-250S |
| 廠商： | PMC-Sierra, Inc. |
| 英文描述： | RM7000⑩ Microprocessor with On-Chip Secondary Cache Datasheet Released |
| 中文描述： | RM7000⑩微處理器與片上二級高速緩存數據發布 |
| 文件頁數： | 34/54頁 |
| 文件大小： | 901K |
| 代理商： | RM7000-250S |
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Proprietary and Confidential to PMC-Sierra, Inc and for its Customer
’
s Internal Use
Document ID: PMC-2002175, Issue 1
34
RM7000
Microprocessor with On-Chip Secondary Cache Datasheet
Released
Table 10 Performance Counter Control
PerfControl
Field
Description
The performance counter interrupt will only occur when interrupts are enabled in the
Status
register, IE=1, and
Interrupt Mask
bit 13 (
IM[13]
) of the coprocessor 0 interrupt control register is
not set.
4..0
Event Type
00:
01:
02:
03:
04:
05:
06:
07:
08:
09:
0A:
0B:
0C:
0D:
0E:
0F:
10:
11:
12:
13:
14:
15:
Clock cycles
Total instructions issued
Floating-point instructions issued
Integer instructions issued
Load instructions issued
Store instructions issued
Dual issued pairs
Branch prefetches
External Cache Misses
Stall cycles
Secondary cache misses
Instruction cache misses
Data cache misses
Data TLB misses
Instruction TLB misses
Joint TLB instruction misses
Joint TLB data misses
Branches taken
Branches issued
Secondary cache writebacks
Primary cache writebacks
Dcache miss stall cycles (cycles where both cache miss tokens taken and a third
address is requested)
Cache misses
FP possible exception cycles
Slip Cycles due to multiplier busy
Coprocessor 0 slip cycles
Slip cycles doe to pending non-blocking loads
Write buffer full stall cycles
Cache instruction stall cycles
Multiplier stall cycles
Stall cycles due to pending non-blocking loads - stall start of exception
16:
17:
18:
19:
1A:
1B:
1C:
1D:
1E:
7..5
Reserved (must be zero)
8
Count in Kernel Mode
0:
1:
Disable
Enable
9
Count in User Mode
0:
1:
Disable
Enable
10
Count Enable
0:
1:
Disable
Enable
31..11
Reserved (must be zero)
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