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參數資料
| 型號： | RM7000-250S |
| 廠商： | PMC-Sierra, Inc. |
| 英文描述： | RM7000⑩ Microprocessor with On-Chip Secondary Cache Datasheet Released |
| 中文描述： | RM7000⑩微處理器與片上二級高速緩存數據發布 |
| 文件頁數： | 5/54頁 |
| 文件大小： | 901K |
| 代理商： | RM7000-250S |
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Proprietary and Confidential to PMC-Sierra, Inc and for its Customer
’
s Internal Use
Document ID: PMC-2002175, Issue 1
5
RM7000
Microprocessor with On-Chip Secondary Cache Datasheet
Released
Table of Contents
Legal Information ...........................................................................................................................2
Revision History .............................................................................................................................3
Document Conventions .................................................................................................................4
Table of Contents ..........................................................................................................................5
List of Figures ................................................................................................................................7
List of Tables .................................................................................................................................8
1
Features ..................................................................................................................................9
2
Block Diagram .......................................................................................................................10
3
Description ............................................................................................................................11
4
Hardware Overview ...............................................................................................................12
4.1
CPU Registers .............................................................................................................12
4.2
Superscalar Dispatch ...................................................................................................12
4.3
Pipeline ........................................................................................................................13
4.4
Integer Unit ..................................................................................................................14
4.5
ALU ..............................................................................................................................15
4.6
Integer Multiply/Divide ..................................................................................................15
4.7
Floating-Point Coprocessor ..........................................................................................16
4.8
Floating-Point Unit .......................................................................................................16
4.9
Floating-Point General Register File ............................................................................16
4.10 System Control Coprocessor (CP0) .............................................................................17
4.11 System Control Coprocessor Registers .......................................................................18
4.12 Virtual to Physical Address Mapping ............................................................................19
4.13 Joint TLB ......................................................................................................................20
4.14 Instruction TLB .............................................................................................................20
4.15 Data TLB ......................................................................................................................20
4.16 Cache Memory .............................................................................................................21
4.17 Instruction Cache .........................................................................................................21
4.18 Data Cache ..................................................................................................................21
4.19 Secondary Cache ........................................................................................................23
4.20 Secondary Caching Protocols ......................................................................................24
4.21 Tertiary Cache .............................................................................................................24
4.22 Cache Locking .............................................................................................................26
4.23 Cache Management .....................................................................................................26
4.24 Primary Write Buffer .....................................................................................................27
4.25 System Interface ..........................................................................................................27
4.26 System Address/Data Bus ...........................................................................................28
4.27 System Command Bus ................................................................................................28
4.28 Handshake Signals ......................................................................................................28
4.29 System Interface Operation .........................................................................................29
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