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參數資料
| 型號： | RM7000-250S |
| 廠商： | PMC-Sierra, Inc. |
| 英文描述： | RM7000⑩ Microprocessor with On-Chip Secondary Cache Datasheet Released |
| 中文描述： | RM7000⑩微處理器與片上二級高速緩存數據發布 |
| 文件頁數： | 17/54頁 |
| 文件大?。?/td> | 901K |
| 代理商： | RM7000-250S |
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Proprietary and Confidential to PMC-Sierra, Inc and for its Customer
’
s Internal Use
Document ID: PMC-2002175, Issue 1
17
RM7000
Microprocessor with On-Chip Secondary Cache Datasheet
Released
Table 5 Floating Point Latencies and Repeat Rates
Latency
Single/double
fadd
4
fsub
4
fmult
4/5
fmadd
4/5
fmsub
4/5
fdiv
21/36
fsqrt
21/36
frecip
21/36
frsqrt
38/68
fcvt.s.d
4
fcvt.s.w
6
fcvt.s.l
6
fcvt.d.s
4
fcvt.d.w
4
fcvt.d.l
4
fcvt.w.s
4
fcvt.w.d
4
fcvt.l.s
4
fcvt.l.d
4
fcmp
1
fmov, fmovc
1
fabs, fneg
1
To support superscalar operations, the FGR has four read ports and two write ports, and is fully
bypassed to minimize operation latency in the pipeline. Three of the read ports and one write port
are used to support the combined multiply-add instruction while the fourth read and second write
port allows a concurrent floating-point load or store and conditional moves.
4.10 System Control Coprocessor (CP0)
The system control coprocessor (CP0) in the MIPS architecture is responsible for the virtual
memory sub-system, the exception control system, and the diagnostics capability of the processor.
In the MIPS architecture, the system control coprocessor (and thus the kernel software) is
implementation dependent. For memory management, the RM7000 CP0 is logically identical to
that of the RM5200 Family and R5000. For interrupt exceptions and diagnostics, the RM7000 is a
superset of the RM5200 Family and R5000 implementing additional features described later in the
sections on Interrupts, the Test/Breakpoint facility, and the Performance Counter facility.
The memory management unit controls the virtual memory system page mapping. It consists of an
instruction address translation buffer (ITLB), a data address translation buffer (DTLB), a Joint
TLB (JTLB), and coprocessor registers used by the virtual memory mapping sub-system.
Operation
Repeat Rate
Single/double
1
1
1/2
1/2
1/2
19/34
19/34
19/34
36/66
1
3
3
1
1
1
1
1
1
1
1
1
1
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PDF描述 |
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| RM7000-250T | RM7000⑩ Microprocessor with On-Chip Secondary Cache Datasheet Released |
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| RM7000-266T | RM7000⑩ Microprocessor with On-Chip Secondary Cache Datasheet Released |
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| RM7000263S | 制造商:QED 功能描述:* |
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| RM7000A | 制造商:PMC 制造商全稱:PMC 功能描述:64-Bit MIPS RISC Microprocessor with Integrated L2 Cache |
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