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參數資料
| 型號： | RM7000-250S |
| 廠商： | PMC-Sierra, Inc. |
| 英文描述： | RM7000⑩ Microprocessor with On-Chip Secondary Cache Datasheet Released |
| 中文描述： | RM7000⑩微處理器與片上二級高速緩存數據發布 |
| 文件頁數： | 25/54頁 |
| 文件大小： | 901K |
| 代理商： | RM7000-250S |
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Proprietary and Confidential to PMC-Sierra, Inc and for its Customer
’
s Internal Use
Document ID: PMC-2002175, Issue 1
25
RM7000
Microprocessor with On-Chip Secondary Cache Datasheet
Released
Figure 7 Tertiary Cache Hit and Miss
Other capabilities of the tertiary interface include block write, tag invalidate, and tag probe. For
details of these transactions as well as detailed timing waveforms for all the tertiary transactions,
see the R5000 or RM7000 Bus Interface Specifications. The tertiary cache tag can easily be
implemented with standard components such as the Motorola MCM69T618.
The RM7000 cache attributes for the instruction, data, internal secondary, and optional external
tertiary caches are summarized in Table 6.
TcDCE*
TcCWE*
TcMatch
SysClock
SysAD
TcLine[17:0]
TcTCE*
Addr
Data1
Data2
Index
Data0
Addr
Data0
Data3
Data1
Data0
Data1
Index
TcWord[1:0]
I0
I1
I2
I0
I3
I0
I1
I2
I3
I1
Master
Processor
Tertiary(Hit)
Tertiary(Miss)
System
Processor
TcDOE*
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| RM7000-250T | RM7000⑩ Microprocessor with On-Chip Secondary Cache Datasheet Released |
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| RM7000263S | 制造商:QED 功能描述:* |
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