- 您現在的位置：買賣IC網 > PDF目錄376314 > RM7000-250S (PMC-Sierra, Inc.) RM7000⑩ Microprocessor with On-Chip Secondary Cache Datasheet Released PDF資料下載
參數資料
| 型號： | RM7000-250S |
| 廠商： | PMC-Sierra, Inc. |
| 英文描述： | RM7000⑩ Microprocessor with On-Chip Secondary Cache Datasheet Released |
| 中文描述： | RM7000⑩微處理器與片上二級高速緩存數據發布 |
| 文件頁數： | 28/54頁 |
| 文件大小： | 901K |
| 代理商： | RM7000-250S |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁當前第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer
’
s Internal Use
Document ID: PMC-2002175, Issue 1
28
RM7000
Microprocessor with On-Chip Secondary Cache Datasheet
Released
Figure 8 Typical Embedded System Block Diagram
4.26 System Address/Data Bus
The 64-bit System Address Data (
SysAD
) bus is used to transfer addresses and data between the
RM7000 and the rest of the system. It is protected with an 8-bit parity check bus,
SysADC
.
The system interface is configurable to allow easy interfacing to memory and I/O systems of
varying frequencies. The data rate and the bus frequency at which the RM7000 transmits data to
the system interface are programmable via boot time mode control bits. Also, the rate at which the
processor receives data is fully controlled by the external device. Therefore, either a low cost
interface requiring no read or write buffering or a faster, high-performance interface can be
designed to communicate with the RM7000. Again, the system designer has the flexibility to make
these price/performance trade-offs.
4.27 System Command Bus
The RM7000 interface has a 9-bit System Command (
SysCmd
) bus. The command bus indicates
whether the
SysAD
bus carries an address or data. If the
SysAD
bus carries an address, then the
SysCmd
bus also indicates what type of transaction is to take place (for example, a read or write).
If the
SysAD
bus carries data, then the SysCmd bus also gives information about the data (for
example, this is the last data word transmitted, or the data contains an error). The
SysCmd
bus is
bidirectional to support both processor requests and external requests to the RM7000. Processor
requests are initiated by the RM7000 and responded to by an external device. External requests are
issued by an external device and require the RM7000 to respond.
The RM7000 supports one to eight byte and 32-byte block transfers on the
SysAD
bus. In the case
of a sub-doubleword transfer, the 3 low-order address bits give the byte address of the transfer, and
the
SysCmd
bus indicates the number of bytes being transferred.
4.28 Handshake Signals
There are ten handshake signals on the system interface. Two of these,
RdRdy*
and
WrRdy*
, are
used by an external device to indicate to the RM7000 whether it can accept a new read or write
RM7000
Memory I/O
Controller
DRAM
Flash/
Boot
ROM
Control
Address
x
x
72
PCI Bus
72
25
Latch
72
8
Tertiary Cache
(optional)
72
SysAD Bus
TcLine, etc.
SysCmd
相關PDF資料 |
PDF描述 |
|---|---|
| RM7000-250T | RM7000⑩ Microprocessor with On-Chip Secondary Cache Datasheet Released |
| RM7000-263S | RM7000⑩ Microprocessor with On-Chip Secondary Cache Datasheet Released |
| RM7000-266T | RM7000⑩ Microprocessor with On-Chip Secondary Cache Datasheet Released |
| RM7000-300S | RM7000⑩ Microprocessor with On-Chip Secondary Cache Datasheet Released |
| RM7000-300T | RM7000⑩ Microprocessor with On-Chip Secondary Cache Datasheet Released |
相關代理商/技術參數 |
參數描述 |
|---|---|
| RM7000263S | 制造商:QED 功能描述:* |
| RM7000-263S | 制造商:QED 功能描述:Microprocessor, 64 Bit, 304 Pin, Plastic, BGA 制造商:Quantum Effect Design 功能描述:Microprocessor, 64 Bit, 304 Pin, Plastic, BGA |
| RM7000-266T | 制造商:QED 功能描述:Microprocessor, 64 Bit, 304 Pin, Plastic, BGA |
| RM7000-300T | 制造商:QED 功能描述: 制造商:QED 功能描述:Microprocessor, 64 Bit, 304 Pin, Plastic, BGA |
| RM7000A | 制造商:PMC 制造商全稱:PMC 功能描述:64-Bit MIPS RISC Microprocessor with Integrated L2 Cache |
發布緊急采購，3分鐘左右您將得到回復。