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參數資料
| 型號： | RM7000-250S |
| 廠商： | PMC-Sierra, Inc. |
| 英文描述： | RM7000⑩ Microprocessor with On-Chip Secondary Cache Datasheet Released |
| 中文描述： | RM7000⑩微處理器與片上二級高速緩存數據發布 |
| 文件頁數： | 42/54頁 |
| 文件大小： | 901K |
| 代理商： | RM7000-250S |
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Proprietary and Confidential to PMC-Sierra, Inc and for its Customer
’
s Internal Use
Document ID: PMC-2002175, Issue 1
42
RM7000
Microprocessor with On-Chip Secondary Cache Datasheet
Released
Table 20
Interrupt Interface Pins
Pin Name
Int*(9:0)
Table 21
JTAG Interface Pins
Pin Name
JTDI
Table 22
Initialization Interface Pins
Pin Name
Type
BigEndian
Input
Type
Input
Description
Interrupt
Ten general processor interrupts, bit-wise ORed with bits 9:0 of the
interrupt register.
Non-maskable interrupt
Non-maskable interrupt, ORed with bit 15 of the interrupt register (bit 6
in R5000 compatibility mode).
NMI*
Input
Type
Input
Description
JTAG data in
JTAG serial data in.
JTAG clock input
JTAG serial clock input.
JTAG data out
JTAG serial data out.
JTAG command
JTAG command signal, signals that the incoming serial data is
command data.
JTCK
Input
JTDO
Output
JTMS
Input
Description
Big Endian / Little Endian Control
Allows the system to change the processor addressing mode without
rewriting the mode ROM.
Vcc is OK
When asserted, this signal indicates to the RM7000 that the 2.5V
power supply has been above 2.25V for more than 100 milliseconds
and will remain stable. The assertion of VccOK initiates the reading of
the boot-time mode control serial stream.
Cold Reset
This signal must be asserted for a power on reset or a cold reset.
ColdReset must be de-asserted synchronously with SysClock.
Reset
This signal must be asserted for any reset sequence. It may be
asserted synchronously or asynchronously for a cold reset, or
synchronously to initiate a warm reset. Reset must be de-asserted
synchronously with SysClock.
Boot Mode Clock
Serial boot-mode data clock output at the system clock frequency
divided by two hundred and fifty six.
Boot Mode Data In
Serial boot-mode data input.
VccOK
Input
ColdReset*
Input
Reset*
Input
ModeClock
Output
ModeIn
Input
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| RM7000-250T | RM7000⑩ Microprocessor with On-Chip Secondary Cache Datasheet Released |
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