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參數資料
| 型號： | RM7000-250S |
| 廠商： | PMC-Sierra, Inc. |
| 英文描述： | RM7000⑩ Microprocessor with On-Chip Secondary Cache Datasheet Released |
| 中文描述： | RM7000⑩微處理器與片上二級高速緩存數據發布 |
| 文件頁數： | 29/54頁 |
| 文件大小： | 901K |
| 代理商： | RM7000-250S |
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Proprietary and Confidential to PMC-Sierra, Inc and for its Customer
’
s Internal Use
Document ID: PMC-2002175, Issue 1
29
RM7000
Microprocessor with On-Chip Secondary Cache Datasheet
Released
transaction. The RM7000 samples these signals before deasserting the address on read and write
requests.
ExtRqst*
and
Release*
are used to transfer control of the
SysAD
and
SysCmd
buses from the
processor to an external device. When an external device needs to control the interface, it asserts
ExtRqst*
. The RM7000 responds by asserting
Release*
to release the system interface to slave
state.
PRqst*
and
PAck*
are used to transfer control of the
SysAD
and
SysCmd
buses from the external
agent to the processor. These two pins are new to the interface relative to the RM52x, R4000 and
R5000 families and have been added to support multiple outstanding reads and ultimately the non-
blocking caches. When the processor needs to reacquire control of the interface, it asserts PRqst*.
The external device responds by asserting PAck* to return control of the interface to the processor.
RspSwap*
is also a new pin and is used by the external agent to tell the processor when it is
returning data out of order; i.e., when there are two outstanding reads, the external agent asserts
RspSwap*
when it is going to return the data for the second read before it returns the data for the
first read.
RspSwap*
must be asserted by the external agent two cycles ahead of when it presents
data so that the processor has time to switch to the correct address for writes into the tertiary cache.
RdType
is the last new pin on the interface.
RdType
indicates whether a read is an instruction read
or a data read. When asserted the reference is an instruction read, when deasserted it is a data read.
RdType
is only valid during valid address cycles.
ValidOut*
and
ValidIn*
are used by the RM7000 and the external device respectively to indicate
that there is a valid command or data on the
SysAD
and
SysCmd
buses. The RM7000 asserts
ValidOut*
when it is driving these buses with a valid command or data, and the external device
drives
ValidIn*
when it has control of the buses and is driving a valid command or data.
4.29 System Interface Operation
Unlike the R4000 and R5000 processor families, to support the non-blocking caches and data
Prefetch instructions, the RM7000 allows two outstanding reads. An external device may respond
to read requests in whatever order it chooses by using the response order indicator pin
RspSwap*
.
No more than two read requests will be submitted to the external device. Other than support for
two outstanding reads, operation of the system interface is identical to that of the RM5270,
RM5271 and R5000. Support for multiple outstanding reads can be enabled or disabled via a boot-
time mode bit.
The RM7000 can issue read and write requests to an external device, while an external device can
issue null and write requests to the RM7000.
For processor reads, the RM7000 asserts
ValidOut*
and simultaneously drives the address and
read command on the
SysAD
and
SysCmd
buses. If the system interface has
RdRdy*
asserted,
then the processor tristates its drivers and releases the system interface to slave state by asserting
Release*
. The external device can then begin sending data to the RM7000.
Figure 9 shows a processor block read request and the external agent read response for a system
with either no tertiary cache or a transaction where the tertiary is being bypassed.
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PDF描述 |
|---|---|
| RM7000-250T | RM7000⑩ Microprocessor with On-Chip Secondary Cache Datasheet Released |
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| RM7000-266T | RM7000⑩ Microprocessor with On-Chip Secondary Cache Datasheet Released |
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| RM7000263S | 制造商:QED 功能描述:* |
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