- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄365968 > TSB14AA1I FPGA (Field-Programmable Gate Array) PDF資料下載
參數(shù)資料
| 型號： | TSB14AA1I |
| 英文描述： | FPGA (Field-Programmable Gate Array) |
| 中文描述： | 電信提供商/數(shù)據(jù)通信 |
| 文件頁數(shù)： | 18/35頁 |
| 文件大小： | 224K |
| 代理商： | TSB14AA1I |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁當(dāng)前第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁
5
–
1
5 Application Information
5.1
Transceiver Selection
The system designer must select transceivers appropriate for the TSB14AA1A and the link layer selected. The
following are requirements for the transceivers needed:
The transceivers used must be appropriate to the backplane technology used.
–
The various backplane technologies require different electrical characteristics in their backplanes. For
example, gunning transceiver logic (GTL) uses an operating voltage on the backplane of 1.2 V and a
characteristic impedance of 50
[1] while low-voltage differential signaling (LVDS) uses an operating
voltage of 2.4 V and a difference impedance of 100
[2]. If a backplane is designed to use GTL
technology, then it would be appropriate to also use that technology for the two lines dedicated to the
1394 serial bus. The drivers selected also must be able to supply the current required for the expected
backplane loading. For example, backplane transceiver logic (BTL) operates correctly for a FutureBus+
[3] configuration backplane at 50 Mbits/s or for a limited number of nodes in a custom configuration at
100 Mbits/s.
The transceivers used must be able to monitor the bus and drive the bus at the same time.
–
During arbitration, each node that is arbitrating for the bus drives its priority code and then its node
number out onto the bus. During each bit period, each node reads back what has been placed on the
bus. If it reads the same data it was sending, the arbitrating node stays in contention for winning the bus.
If it reads something different than what it was driving, the arbitrating node loses the bus and drops out of
contention. As long as each node is still sending 0s onto the bus during arbitration, all nodes are still
contending to win the bus. The node with the highest priority (or if all priorities were 0, then the highest
node number) is the first to drive a 1 onto the bus during arbitration. The node that sends the first 1
(asserting the bus) and reads it back wins the bus. All other nodes read back a 1, which does not match
the 0 (releasing the bus) they are sending, and drop out of contention. This arbitration process requires
the transceiver selected to be able to read from the bus at the same time it is driving the bus.
The transceivers used must be appropriate for the transfer speed required.
–
The 1394 bus has two data lines that use data-strobe encoding on the bus. This requires that the
transceivers be able to operate at a maximum frequency of one half of the maximum data transfer rate.
When operating at 49.152 Mbits/s, the maximum frequency the drivers are required to operate at is
24.576 MHz. When operating at 98.304 Mbits/s, the maximum frequency the drivers are required to
operate at is 49.152 MHz.
Recommended transceivers:
–
When the designer has a choice of transceiver, the open collector transceiver SN74GTLP1394 [4] is
recommended. This is the device used to verify lab operation at both S50 and S100 data rates.
–
When the designer must choose a differential transceiver, the 3-state transceiver SN65LVDM176 [5] is
recommended. This device was also used to verify lab operation at both S50 and S100 data rates.
[1]
GTL/BTL a Low Swing Solution for High-Speed Digital Logic
(SCEA003)
(2]
Low-Voltage Differential Signaling (LVDS) Design Notes
(SLLA014)
[3] IEEE Std 896.1
–
1991,
IEEE Standard for FutureBus+
—
Logical Protocol Specification
[4]
SN74GTLP1394, 2-Bit LVTLL-to-GTLP Adjustable-Edge Rate Bus Transceiver With Selectable Polarity
data sheet (SCES286A)
[5]
SN65LVDM176, High-Speed Differential Line Transceiver
data sheet (SLLS320D)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TSB14AA1T | FPGA (Field-Programmable Gate Array) |
| TSB14C01MHV | IC APEX 20KE FPGA 160K 484-FBGA |
| TSB14C01HV | 5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER |
| TSB21LV03MHV | IC APEX 20KE FPGA 200K 484-FBGA |
| TSB21LV03CHV | IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSB14AA1PFB | 功能描述:1394 接口集成電路 3.3V 1-port 50/100 Mbps Backplane PHY RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB14AA1PFBG4 | 功能描述:1394 接口集成電路 3.3V 1-port 50/100 Mbps Backplane PHY RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB14AA1T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecomm/Datacomm |
| TSB14AA1TPFB | 功能描述:IC BACKPLANE PHY 3.3V 48-TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
| TSB14C01 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。