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參數資料
| 型號： | TSB14AA1I |
| 英文描述： | FPGA (Field-Programmable Gate Array) |
| 中文描述： | 電信提供商/數據通信 |
| 文件頁數： | 28/35頁 |
| 文件大小： | 224K |
| 代理商： | TSB14AA1I |
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6
–
8
6.2.4
Backplane Transmit Data Timing
Edge separation is the minimum required time between any two consecutive transitions of the backplane bus signals,
as they appear from the output of the transmitters, whether they are transitions on the same signal or transitions on
the two separate signals. A minimum edge separation is required to ensure proper operation of the data strobe
bit-level encoding mechanism. TDATA and TSTRB have the relationship shown in Figure 6
–
7 and Table 6
–
10.
t(2)
t(2)
t(1)
TDATA
TSTRB
t(2)
t(2)
t(1)
t(1)
t(1)
Figure 6
–
7. Minimum Edge Separation
Table 6
–
10. TSB14AA1A to Backplane Transceiver Timing
PARAMETER
98.304 MHz
49.152 MHz
t(1)
t(2)
This parameter is based on a maximum total transmit skew of 2 ns.
Bit cell period for data
9.44 ns minimum
19.44 ns minimum
Transmit (Tx) edge separation
8.65 ns minimum
18.65 ns minimum
6.2.5
Backplane Receive Data Timing
The receiver typically uses the transitions on the incoming bus signals RDATA and RSTRB to derive a clock at the
code bit frequency to extract the NRZ signal on RDATA. This clock can be derived by performing an exclusive-OR
(XOR) of RDATA and RSTRB.
The bus signals, as they appear from the backplane transceiver media and into the receiver, should fall within the
timing constraints outlined by Figure 6
–
8.
RDATA
RSTRB
t(3)
t(1)
t(1)
t(1)
t(1)
t(2)
t(3)
t(2)
Figure 6
–
8. Backplane Receive Data Timing
Table 6
–
11. TSB14AA1A to Backplane Transceiver Timing
PARAMETER
98.304 MHz
49.152 MHz
t(1)
t(2)
t(3)
This parameter is based on a maximum total transmit skew of 2 ns and a maximum backplane skew of 0.5 ns.
This assumes total receive skew is less than receive edge separation (i.e., some skew margin exists).
Bit cell period
10.1715 ns nominal
20.34 nominal
Receive (Rx) edge separation
3.4 ns minimum
16.3 ns maximum
3.4 ns minimum
36.6 ns maximum
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PDF描述 |
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| TSB14AA1T | FPGA (Field-Programmable Gate Array) |
| TSB14C01MHV | IC APEX 20KE FPGA 160K 484-FBGA |
| TSB14C01HV | 5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER |
| TSB21LV03MHV | IC APEX 20KE FPGA 200K 484-FBGA |
| TSB21LV03CHV | IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER |
相關代理商/技術參數 |
參數描述 |
|---|---|
| TSB14AA1PFB | 功能描述:1394 接口集成電路 3.3V 1-port 50/100 Mbps Backplane PHY RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB14AA1PFBG4 | 功能描述:1394 接口集成電路 3.3V 1-port 50/100 Mbps Backplane PHY RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB14AA1T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecomm/Datacomm |
| TSB14AA1TPFB | 功能描述:IC BACKPLANE PHY 3.3V 48-TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標準包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應商設備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
| TSB14C01 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER |
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