- 您現在的位置：買賣IC網 > PDF目錄365968 > TSB14AA1I FPGA (Field-Programmable Gate Array) PDF資料下載
參數資料
| 型號： | TSB14AA1I |
| 英文描述： | FPGA (Field-Programmable Gate Array) |
| 中文描述： | 電信提供商/數據通信 |
| 文件頁數： | 29/35頁 |
| 文件大小： | 224K |
| 代理商： | TSB14AA1I |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁當前第29頁第30頁第31頁第32頁第33頁第34頁第35頁
6
–
9
6.2.6
Backplane Timing Definitions
Logic Skew
—
The skew between data and strobe within the physical layer itself due to internal skews
between data and strobe logic.
Spatial Skew
—
The skew between data and strobe due to differences in propagation delays along the
transmission line from the arbiter to the transceiver.
Package Skew
—
The propagation delay difference through the transceiver between the data and strobe
channels.
Backplane Skew
—
The skew along the backplane itself due to impedance and/or mismatched data and
strobe line length.
Receive Setup/Hold
—
The setup and hold time needed to latch the incoming data within the PHY arbiter,
based on the recovered clock from Data_Rx and Strb_Rx.
Total Transmit Skew
—
The total skew between data and strobe in transmitting data from the PHY out to the
bus. This is given by the following equation:
Total Transmit Skew = Transmit Package Skew + Spatial Skew + Logic Skew
Total Receive Skew
—
The total skew between data and strobe in receiving data from the bus into the PHY.
This is given by the following equation:
Total Receive Skew = Receive Package Skew + Spatial Skew + Receive Setup + Receive Hold
Skew Margin
—
The bit cell period minus all skews. This is given by the following equation:
Skew Margin = Bit Cell Period
–
Total Transmit Skew
–
Backplane Skew
–
Total Receive Skew
Transmit Edge Separation
—
The minimum time required between any two consecutive transitions of the
bus signals to ensure proper operation of data-strobe bit level encoding. Transmit edge separation is
measured from the midpoint of the signal transition to the midpoint of the next signal transition out on the
bus. Minimum transmit edge separation is the minimum bit cell period less the maximum total transmit skew.
Receive Edge Separation
—
The minimum time required between any two consecutive transitions of the bus
signals to ensure proper operation of data-strobe bit level decoding. Receive edge separation is measured
from the midpoint of the signal transition to the midpoint of the next signal transition out on the bus. This
is the minimum bit cell period reduced by the amount of maximum total transmit skew and maximum
backplane skew.
6.2.7
Gap Timing
A gap is a period of time during which the bus is idle (Data_Rx and Strb_Rx are unasserted). There are three types
of gaps:
Acknowledge Gap
—
Appears between the end of a packet and an acknowledge, as well as between
isochronous transfers. A node should detect the occurrence of an acknowledge gap after the bus has been
in an unasserted state for 4 arbitration clock times (approximately 81.38 ns) but should not assert the bus
until a total of 8 arbitration clock times (approximately 182.76 ns) have occurred. This requirement ensures
that a node is given adequate time to detect the acknowledge gap before the bus is asserted by another
node upon detecting an acknowledge gap. This includes the minimum time required to detect a Bus_Idle
(4 arbitration clock times), as well as the maximum delay between the arbitration state machine within any
two nodes on the bus (another 4 arbitration clock times).
Subaction Gap
—
Appears before asynchronous transfers within a fairness interval. A node should detect
the occurrence of a subaction gap after the bus has been in an unasserted state for at least 16 arbitration
clock times (approximately 325.52 ns), but should not assert the bus until a total of 20 arbitration clock times
(approximately 406.9 ns) have occurred. This requirement ensures that a node is given adequate time to
相關PDF資料 |
PDF描述 |
|---|---|
| TSB14AA1T | FPGA (Field-Programmable Gate Array) |
| TSB14C01MHV | IC APEX 20KE FPGA 160K 484-FBGA |
| TSB14C01HV | 5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER |
| TSB21LV03MHV | IC APEX 20KE FPGA 200K 484-FBGA |
| TSB21LV03CHV | IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER |
相關代理商/技術參數 |
參數描述 |
|---|---|
| TSB14AA1PFB | 功能描述:1394 接口集成電路 3.3V 1-port 50/100 Mbps Backplane PHY RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB14AA1PFBG4 | 功能描述:1394 接口集成電路 3.3V 1-port 50/100 Mbps Backplane PHY RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB14AA1T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecomm/Datacomm |
| TSB14AA1TPFB | 功能描述:IC BACKPLANE PHY 3.3V 48-TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標準包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應商設備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
| TSB14C01 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER |
發布緊急采購，3分鐘左右您將得到回復。