
5.2 Overview
5.2.1
Device Initialization
5.2.1.1 Reset
TSC2117
Low-Power Audio Codec With Embedded miniDSP, Stereo Class-D
Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller
SLAS550A – APRIL 2009 – REVISED JUNE 2009
www.ti.com
The TSC2117 is a highly integrated stereo audio DAC and monaural ADC with touch-screen controller for
portable computing, communication, and entertainment applications. A register-based architecture eases
integration with microprocessor-based systems through standard serial-interface buses. This device
supports the four-wire SPI bus and the 2-wire I2C bus interfaces. The I2C interface and the SPI interface
provide full register access. The SPI data bus can be used for higher-speed communication and for
high-speed retrieval of SAR ADC data. All peripheral functions are controlled through these registers and
the onboard state machines.
The TSC2117 consists of the following blocks:
Touch-panel drivers
Microphone interfaces (analog and digital)
Audio codec (mono ADC and stereo DAC)
AGC and DRC
Two miniDSP digital signal-processing blocks (record and playback paths)
Beep generator
Stereo headphone/lineout amplifier
Class-D stereo amplifier for 8- speakers
Pin-controlled or register-controlled volume level
Power-down de-pop and power-up soft start
SAR ADC for touch-panel, voltage, and temperature measurements
FIFO buffer mode for SAR auxiliary and touch-screen data
Auxiliary inputs
SPI control interface
I2C control interface
Power-down control block
Following a toggle of the RESET pin or a software reset, the device operates in the default mode. The SPI
or I2C interface can be used to write to the control registers to configure the device.
The I2C address assigned to the TSC2117 is 001 1000. This device always operates in an I2C slave
mode. All registers are 8-bit, and all writable registers have read-back capability. The device
auto-increments to support sequential addressing and can be used with I2C fast mode. Once the device is
reset, all appropriate registers are updated by the host processor to configure the device as needed by the
user.
SAR ADC data is transferred though the SPI/I2C bus, and audio data (for audio ADC and DAC) is
transferred through the audio serial interface. The SPI interface requires that the SS signal be driven low
to communicate with the TSC2117. Data is then shifted into or out of the TSC2117 under control of the
host microprocessor, which also provides the SPI serial clock.
The TSC2117 internal logic must be initialized to a known condition for proper device function. To initialize
the device to its default operating condition, the hardware reset pin (RESET) must be pulled low for at
least 10 ns. For this initialization to work, both the IOVDD and DVDD supplies must be powered up. It is
recommended that while the DVDD supply is being powered up, the RESET pin be pulled low.
The device can also be reset via software reset. Writing a 1 into page 0/register 1, bit D0 resets the
device.
APPLICATION INFORMATION
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