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參數資料
| 型號： | TSC2117IRGZT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, QCC48 |
| 封裝： | 7 X 7 MM, GREEN, PLASTIC, VQFN-48 |
| 文件頁數： | 6/192頁 |
| 文件大小： | 2728K |
| 代理商： | TSC2117IRGZT |
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DA(6)
DA(0)
RA(7)
RA(0)
D(7)
D(0)
Start
(M)
7-bitDevice Address
(M)
Write
(M)
Slave
Ack
(S)
8-bitRegister Address
(M)
Slave
Ack
(S)
8-bitRegisterData
(M)
Stop
(M)
Slave
Ack
(S)
SDA
SCL
(M)=>SDA ControlledbyMaster
(S)=>SDA ControlledbySlave
Start
(M)
7-bitDevice Address
(M)
Write
(M)
Slave
Ack
(S)
8-bitRegister Address
(M)
Slave
Ack
(S)
SDA
SCL
7-bitDevice Address
(M)
Read
(M)
Slave
Ack
(S)
DA(6)
DA(0)
RA(7)
RA(0)
DA(6)
DA(0)
D(7)
D(0)
8-bitRegisterData
(S)
Stop
(M)
Master
No Ack
(M)
Repeat
Start
(M)
(M)=>SDA ControlledbyMaster
(S)=>SDA ControlledbySlave
5.9.3.2 SPI Digital Interface
TSC2117
Low-Power Audio Codec With Embedded miniDSP, Stereo Class-D
Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller
www.ti.com
SLAS550A – APRIL 2009 – REVISED JUNE 2009
The TSC2117 can also respond to and acknowledge a General Call, which consists of the master issuing
a command with a slave address byte of 00H. This feature is disabled by default, but can be enabled via
page 0/register 34, bit D5.
Figure 5-73. I2C Write
Figure 5-74. I2C Read
In the case of an I2C register write, if the master does not issue a STOP condition, then the device enters
auto-increment mode. So in the next eight clocks, the data on SDA is treated as data for the next
incremental register.
Similarly, in the case of an I2C register read, after the device has sent out the 8-bit data from the
addressed register, if the master issues a ACKNOWLEDGE, the slave takes over control of SDA bus and
transmit for the next 8 clocks the data of the next incremental register.
In the SPI control mode, the TSC2117 uses the pins SCLK, SS, MISO, and MOSI as a standard SPI port
with clock polarity setting of 0 (typical microprocessor SPI control bit CPOL = 0). The SPI port allows
full-duplex, synchronous, serial communication between a host processor (the master) and peripheral
devices (slaves). The SPI master (in this case, the host processor) generates the synchronizing clock
(driven onto SCLK) and initiates transmissions. The SPI slave devices (such as the TSC2117) depend on
a master to start and synchronize transmissions. A transmission begins when initiated by an SPI master.
The byte from the SPI master begins shifting in on the slave MOSI pin under the control of the master
serial clock (driven onto SCLK). As the byte shifts in on the MOSI pin, a byte shifts out on the MISO pin to
the master shift register.
The TSC2117 interface is designed so that with a clock-phase bit setting of 1 (typical microprocessor SPI
control bit CPHA = 1), the master begins driving its MOSI pin and the slave begins driving its MISO pin on
the first serial clock edge. The SS pin can remain low between transmissions; however, the TSC2117 only
interprets the first 8 bits transmitted after the falling edge of SS as a command byte, and the next 8 bits as
a data byte only if writing to a register. Reserved register bits should be written to their default values. The
TSC2117 is entirely controlled by registers. Reading and writing these registers is accomplished by an
8-bit command sent to the MOSI pin of the part prior to the data for that register. The command is
structured as shown in Section 5.9.3.3. The first 7 bits specify the register address which is being written
or read, from 0 to 127 (decimal). The command word ends with an R/W bit, which specifies the direction of
APPLICATION INFORMATION
103
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