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參數資料
| 型號： | TSC2117IRGZT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, QCC48 |
| 封裝： | 7 X 7 MM, GREEN, PLASTIC, VQFN-48 |
| 文件頁數： | 137/192頁 |
| 文件大小： | 2728K |
| 代理商： | TSC2117IRGZT |
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5.6.1.3 DAC User-Programmable Filters
1
0
1
15
1
N
N z
H(z)
2
D z
-
+
=
-
(5-4)
TSC2117
Low-Power Audio Codec With Embedded miniDSP, Stereo Class-D
Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller
www.ti.com
SLAS550A – APRIL 2009 – REVISED JUNE 2009
Depending on the selected processing block, different types and orders of digital filtering are available. Up
to six biquad sections are available for specific processing blocks.
The coefficients of the available filters are arranged as sequentially-indexed coefficients in two banks. If
adaptive filtering is chosen, the coefficient banks can be switched on-the-fly.
When the DAC is running, the user-programmable filter coefficients are locked and cannot be accessed
for either read or write.
However the TSC2117 offers an adaptive filter mode as well. Setting page 8/register 1, bit D2 = 1 turns on
double buffering of the coefficients. In this mode, filter coefficients can be updated through the host and
activated without stopping and restarting the DAC. This enables advanced adaptive filtering applications.
In the double-buffering scheme, all coefficients are stored in two buffers (buffers A and B). When the DAC
is running and adaptive filtering mode is turned on, setting page 8/register 1, bit D0 = 1 switches the
coefficient buffers at the next start of a sampling period. This bit is set back to 0 after the switch occurs. At
the same time, page 8/register 1, bit D1 toggles.
The flag in page 8/register 1, bit D1 indicates which of the two buffers is actually in use.
Page 8/register 1, bit D1 = 0: buffer A is in use by the DAC engine; bit D1 = 1: buffer B is in use.
While the device is running, coefficient updates are always made to the buffer not in use by the DAC,
regardless of the buffer to which the coefficients have been written.
Table 5-25. Adaptive-Mode Filter-Coefficient Buffer Switching
DAC Running?
Page 8, Reg 1, D(1)
Coefficient Buffer in Use
Writing to
Updates
No
0
None
C1, buffer A
No
0
None
C1, buffer B
Yes
0
Buffer A
C1, buffer A
C1, buffer B
Yes
0
Buffer A
C1, buffer B
Yes
1
Buffer B
C1, buffer A
Yes
1
Buffer B
C1, buffer B
C1, buffer A
The user-programmable coefficients C1 to C70 are defined on pages 8, 9, 10, and 11 for buffer A and
pages 12, 13, 14, and 15 for buffer B.
The coefficients of these filters are each 16-bit, 2s-complement format, occupying two consecutive 8-bit
registers in the register space. Specifically, the filter coefficients are in 1.15 (one dot 15) format with a
range from –1.0 (0x8000) to 0.999969482421875 (0x7FFF) as shown in Figure 5-12.
5.6.1.3.1 First-Order IIR Section
The IIR is of first order and its transfer function is given by
The frequency response for the first-order IIR section with default coefficients is flat.
Table 5-26. DAC IIR Filter Coefficients
DAC Coefficient,
Filter
Filter Coefficient
Default (Reset) Values
Left Channel
Right Channel
First-order IIR
N0
Page 9/registers 2–3
Page 9/registers 8–9
0x7FFF (decimal 1.0 – LSB
value)
N1
Page 9/registers 4–5
Page 9/registers 10–11
0x0000
D1
Page 9/registers 6–7
Page 9/registers 12–13
0x0000
APPLICATION INFORMATION
49
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