
Programmedfor
Host-Controlled
ModeWithInvalid
A/DFunction
Selected
DetectingTouch
WaitingforHostto
WriteIntoP3/R3
P3/R3
IsUpdated
forContinous
AUXSCAN
Mode
Reading
AUX-Data
Register
Sample,Conversion
and Averagingfor
AUXinput
PINTDAV (As
[P3/R3,D1–D0=01])
DATA_AVA
CONTROL INTERFACEDEACTIVATED
Reading
AUX-Data
Register
Sample,Conversion
and Averagingfor
AUXinput
Sample,Conversion
and Averagingfor
AUXinput
WaitforReferencePower-UpDelayinCase
ofInternalReferenceModeif Applicable
5.7.9.4 Port-Scan Operation
(
)
(
)
AVG
BITS
CONV
AVG
1
CLK
2
CLK
t
3
N
1
t
3
N
n
13
t
35
t
n
t
=
+
+
+
+
+
DetectingTouch
Sample,Conversionand
AveragingforBAT1
andBAT2and AUXInput
Programmedfor
Host-Controlled
ModeWithInvalid
A/DFunction
Selected
P3/R3
IsUpdated
for
PORTSCAN
Mode
CONTROL INTERFACEDEACTIVATED
Reading
AUX-Data
Register
Reading
BAT2-
Data
Register
Reading
BAT1-
Data
Register
WaitingforHostto
WriteIntoP3/R3
WaitforReferencePower-UpDelayinCase
ofInternalReferenceModeif Applicable
WaitingforHostto
WriteIntoP3/R3
PINTDAV (As
[P3/R3,D1–D0=01])
DATA_AVA
5.8 CLOCK Generation and PLL
TSC2117
Low-Power Audio Codec With Embedded miniDSP, Stereo Class-D
Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller
www.ti.com
SLAS550A – APRIL 2009 – REVISED JUNE 2009
Figure 5-56. Host-Controlled Continuous Aux Scan Mode
The time needed to complete one set of port-scan conversions is given by:
(1)
This equation is valid if page 2/register 18, bits D6–D5 = 00, which means SAR data update is not kept on hold for reading converted
data.
(2)
This equation is valid if page 3/register 6, bit D0 = 1.
(3)
The programmable delay tREF scales accordingly based on the actual divider setting and time period of theclock used to generate
this. See the respective control register settings to understand the scale factors.
where:
DIV1 = Divider setting as configured in page 3/register 2, bits D4–D3
NBITS = SAR ADC resolution as configured in page 3/register 2, bits D6–D5
n1 = 6 if DIV1 = 1; otherwise, n1 = 7
n2 = 0 if external reference mode is selected; or 3 if tREF = 0 ms or internal reference is powered up all th
e time; or 1 + tREF/tCLK if tREF is not equal to 0 ms and internal reference must power down between conv
ersions
tREF = Internal reference stablization time as configured in page 3/register 6, bits D3–D2.
Figure 5-57. Host-Controlled Port Scan Mode
The TSC2117 supports a wide range of options for generating clocks for the ADC and DAC sections as
well as interface and other control blocks as shown in
Figure 5-58. The clocks for ADC and DAC require a
source reference clock. This clock can be provided on variety of device pins such as MCLK, BCLK, or
GPIO1 pins. The source reference clock for the codec can be chosen by programming the
CODEC_CLKIN value on page 0/register 4, D(1:0). The CODEC_CLKIN can then be routed through
highly-flexible clock dividers shown in
Figure 5-58 to generate the various clocks required for ADC, DAC
APPLICATION INFORMATION
87