
6
REGISTER MAP
6.1 TSC2117 Register Map
6.2 Control Registers, Page 0 (Default Page): Clock Multipliers, Dividers, Serial Interfaces,
TSC2117
Low-Power Audio Codec With Embedded miniDSP, Stereo Class-D
Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller
www.ti.com
SLAS550A – APRIL 2009 – REVISED JUNE 2009
All features on this device can be addressed using the I2C bus or the SPI bus. However, it is not
recommended to use the I2C bus and the SPI bus simultaneously for updating register values. All
of the writable registers can be read back. However, some registers contain status information or data,
and are available for reading only.
The TSC2117 contains several pages of 8-bit registers, and each page can contain up to 128 registers.
The register pages are divided up based on functional blocks for this device. The pages defined for the
TSC2117 are 0, 1, 3, 4–5 (ADC coefficient pages), and 8–15 (DAC coefficient pages), 32–43 (ADC IRAM
pages), 64–95 (DAC IRAM pages), and 252 (SAR buffer data page). Page 0 is the default home page
after RESET. Page control is done by writing a new page value into register 0 of the current page.
The control registers for the TSC2117 are described in detail as follows. All registers are 8 bits in width,
with D7 referring to the most-significant bit of each register, and D0 referring to the least-significant bit.
Pages 0, 1, 3, 4–5, 8–15, 32–43, 64–95, and 252 are available. All other pages are reserved. Do not read
from or write to reserved pages and registers. Also, do not write other than the reset values for the
reserved bits and read-only bits of non-reserved registers; otherwise, device functionality failure can occur.
Table 6-1. Summary of Register Map
Page Number
Description
Page 0 is the default page on power up. Configuration for serial interface, digital I/O, clocking, ADC, DAC miniDSP
0
settings, etc.
1
Configuration for analog PGAs, ADC, DAC, output drivers, volume controls, etc.
3
Configuration for 12-bit SAR converter settings and touch-screen settings
4-5
ADC AGC and filter coefficients
8-15
DAC filter and DRC coefficients
32-43
ADC instruction RAM locations
64-95
DAC instruction RAM locations
252
SAR ADC buffer mode read data
Flags, Interrupts, and GPIOs
Page 0/Register 0: Page Control Register
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D0
R/W
0000 0000
0000 0000: Page 0 selected
0000 0001: Page 1 selected
...
1111 1110: Page 254 selected
1111 1111: Page 255 selected
Page 0/Register 1: Software Reset
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D1
R/W
0000 000
Reserved. Write only zeros to these bits.
D0
R/W
0
0: Don't care
1: Self-clearing software reset for control register
REGISTER MAP
105