- 您現在的位置：買賣IC網 > PDF目錄98302 > TSC2117IRGZT (TEXAS INSTRUMENTS INC) SPECIALTY CONSUMER CIRCUIT, QCC48 PDF資料下載
參數資料
| 型號： | TSC2117IRGZT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, QCC48 |
| 封裝： | 7 X 7 MM, GREEN, PLASTIC, VQFN-48 |
| 文件頁數： | 186/192頁 |
| 文件大小： | 2728K |
| 代理商： | TSC2117IRGZT |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁當前第186頁第187頁第188頁第189頁第190頁第191頁第192頁
5.9.1.1 Right-Justified Mode
BCLK
WCLK
SDIN/SDOUT
n-1 n-2
1
0
n-1 n-2
1
0
LSB
MSB
LeftChannel
RightChannel
n-3
2
n-3
LSB
MSB
1/fs
TSC2117
Low-Power Audio Codec With Embedded miniDSP, Stereo Class-D
Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller
www.ti.com
SLAS550A – APRIL 2009 – REVISED JUNE 2009
configuring page 0/register 27, D(5:4). In addition, the word clock and bit clock can be independently
configured in either Master or Slave mode, for flexible connectivity to a wide variety of processors. The
word clock is used to define the beginning of a frame, and may be programmed as either a pulse or a
square-wave signal. The frequency of this clock corresponds to the maximum of the selected ADC and
DAC sampling frequencies.
The bit clock is used to clock in and clock out the digital audio data across the serial bus. When in Master
mode, this signal can be programmed to generate variable clock pulses by controlling the bit-clock divider
in page 0/register 30 (see Figure 5-58). The number of bit-clock pulses in a frame may need adjustment to
accommodate various word-lengths as well as to support the case when multiple TSC2117s may share
the same audio bus.
The TSC2117 also includes a feature to offset the position of start of data transfer with respect to the
word-clock. This offset can be controlled in terms of number of bit-clocks and can be programmed in page
0/register 28.
The TSC2117 also has the feature of inverting the polarity of the bit-clock used for transferring the audio
data as compared to the default clock polarity used. This feature can be used independently of the mode
of audio interface chosen. This can be configured via page 0/register 29, D(3).
The TSC2117 further includes programmability (page 0/register 27, D0) to 3-state the SDOUT line during
all bit clocks when valid data is not being sent. By combining this capability with the ability to program at
what bit clock in a frame the audio data begins, time-division multiplexing (TDM) can be accomplished,
enabling the use of multiple codecs on a single audio serial data bus. When the audio serial data bus is
powered down while configured in master mode, the pins associated with the interface are put into a
3-state output condition.
By default when the word-clocks and bit-clocks are generated by the TSC2117, these clocks are active
only when the codec (ADC, DAC or both) are powered up within the device. This is done to save power.
However, it also supports a feature when both the word clocks and bit-clocks can be active even when the
codec in the device is powered down. This is useful when using the TDM mode with multiple codecs on
the same bus, or when word-clock or bit-clocks are used in the system as general-purpose clocks.
The audio interface of the TSC2117 can be put into right-justified mode by programming page 0/register
27, D(7:6) = 10. In right-justified mode, the LSB of the left channel is valid on the rising edge of the bit
clock preceding the falling edge of the word clock. Similarly, the LSB of the right channel is valid on the
rising edge of the bit clock preceding the rising edge of the word clock.
Figure 5-61. Timing Diagram for Right-Justified Mode
For right-justified mode, the number of bit-clocks per frame should be greater than or equal to twice the
programmed word-length of the data.
APPLICATION INFORMATION
93
相關PDF資料 |
PDF描述 |
|---|---|
| TSC2300IPAGG4 | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| TSC2300IPAGR | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| TSC2300IPAG | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| TSC2300IPAGRG4 | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| TSC2301IPAGR | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| TSC2117IRGZT | 制造商:Texas Instruments 功能描述:Touch Screen Controller IC |
| TSC22 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EURO TERMINAL BLOCKS |
| TSC2200 | 制造商:BB 制造商全稱:BB 功能描述:PDA ANALOG INTERFACE CIRCUIT |
| TSC2200EVM | 功能描述:觸摸傳感器開發工具 Touch Screen Contr Eval Mod RoHS:否 制造商:Cypress Semiconductor 工具用于評估: 接口類型: 工作電壓: 最大工作溫度: |
| TSC2200IPW | 功能描述:觸摸屏轉換器和控制器 Prog 4-Wire w/12-Bit 125KHz ADC & Key Ifc RoHS:否 制造商:Microchip Technology 類型:Resistive Touch Controllers 輸入類型:3 Key 數據速率:140 SPS 分辨率:10 bit 接口類型:4-Wire, 5-Wire, 8-Wire, I2C, SPI 電源電壓:2.5 V to 5.25 V 電源電流:17 mA 工作溫度:- 40 C to + 85 C 封裝 / 箱體:SSOP-20 |
發布緊急采購，3分鐘左右您將得到回復。