
TSC2117
Low-Power Audio Codec With Embedded miniDSP, Stereo Class-D
Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller
SLAS550A – APRIL 2009 – REVISED JUNE 2009
www.ti.com
Page 0/Register 32: Codec Secondary Interface Control 2
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D5
R/W
000
000: ADC_WCLK is obtained from GPIO1 pin.
001: ADC_WCLK is obtained from SCLK pin.
010: ADC_WCLK is obtained from MISO pin.
011: Reserved
100: ADC_WCLK is obtained from GPIO2 pin.
101: ADC_WCLK is obtained from GPI1 pin.
110: ADC_WCLK is obtained from GPI2 pin.
111: ADC_WCLK is obtained from GPI3 pin.
D4
R/W
0
Reserved
D3
R/W
0
0: Primary BCLK is fed to codec serial-interface and ClockGen blocks.
1: Secondary BCLK is fed to codec serial-interface and ClockGen blocks.
D2
R/W
0
0: Primary WCLK is fed to codec serial-interface block.
1: Secondary WCLK is fed to codec serial-interface block.
D1
R/W
0
0: ADC_WCLK used in the codec serial-interface block is the same as DAC_WCLK.
1: ADC_WCLK used in the codec serial-interface block = ADC_WCLK.
D0
R/W
0
0: Primary SDIN is fed to codec serial-interface block.
1: Secondary SDIN is fed to codec serial-interface block.
Page 0/Register 33: Codec Secondary Interface Control 3
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7
R/W
0
0: Primary BCLK output = internally generated BCLK clock
1: Primary BCLK output = secondary BCLK
D6
R/W
0
0: Secondary BCLK output = primary BCLK
1: Secondary BCLK output = internally generated BCLK clock
D5–D4
R/W
00
00: Primary WCLK output = internally generated DAC_fS
01: Primary WCLK output = internally generated ADC_fS clock
10: Primary WCLK output = secondary WCLK
11: Reserved
D3–D2
R/W
00
00: Secondary WCLK output = primary WCLK
01: Secondary WCLK output = internally generated DAC_fS clock
10: Secondary WCLK output = internally generated ADC_fS clock
11: Reserved
D1
R/W
0
0: Primary SDOUT = SDOUT from codec serial-interface block
1: Primary SDOUT = secondary SDIN
D0
R/W
0
0: Secondary SDOUT = primary SDIN
1: Secondary SDOUT = SDOUT from codec serial interface block
Page 0/Register 34: I2C Bus Condition
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D6
R/W
00
Reserved. Write only the reset value to these bits.
D5
R/W
0
0: I2C general-call address is ignored.
1: Device accepts I2C general-call address.
D4–D0
R/W
00000
Reserved. Write only zeros to these bits.
Page 0/Register 35: Reserved
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D0
R/W
XXXX XXXX
Reserved. Write only zeros to these bits.
REGISTER MAP
112