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參數(shù)資料
型號: 935269580557
廠商: NXP SEMICONDUCTORS
元件分類: 消費(fèi)家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP100
封裝: PLASTIC, HTQFP-100
文件頁數(shù): 18/84頁
文件大小: 1054K
代理商: 935269580557
Philips Semiconductors
PNX8510/11
Analog Companion Chip
9397 750 08865
Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved.
Product data
Rev. 02 — 8 October 2001
25 of 84
5.
GPIO Block Functional Description
GPIOs are multi-purpose pins. They may be programmed as input/output and used to carry
signals into the IC or to monitor the status of the IC. The selection of these I/O pins is controlled
through programmable registers. The GPIO module can be programmed via subaddress 90-95
of the primary video pipe.
5.1 Overview
The GPIO pins operate in two basic modes: Bootstrap mode and GPIO mode
During chip reset the GPIOs are in bootstrap mode. The status of all GPIO pins is monitored and
used to determine the set of I2C device addresses the IC responds to.
After the chip reset is released, the GPIO pins may be used in GPIO mode. In output mode each
GPIO pin can be set to logic one or zero by programming the appropriate register. In input mode
the status of each GPIO can be monitored by reading the appropriate status register. In addition
to the register-driven I/O mode, some of the GPIO pins are used to reflect the status of internal
signals. Some GPIO pins are also used as additional inputs to functional units if operated in
input mode.
5.2 Operation
GPIO Set During Reset
During reset the GPIO output is disabled. GPIO_in is stored as gpio_in_stored and retains its
value until the next reset. This stored value determines the I2C device addresses. After reset,
GPIO pins can be programmed for output with the OEN and OUT_SEL bits.
The I2C subaddresses are derived from the GPIOs in the following way:
Primary video pipe: {gpio5,gpio4,0,0,gpio3,gpio2,gpio1}
Secondary video pipe: {gpio5,gpio4,0,1,gpio3,gpio2,gpio1}
Primary audio pipe: {gpio5,gpio4,1,0,gpio3,gpio2,gpio1}
Secondary audio pipe: {gpio5,gpio4,1,1,gpio3,gpio2,gpio1}
Checking/Setting the GPIO Status
Each GPIO pin is multiplexed four times to increase usability. The Figure 20 outlines the internal
structure of one GPIO pin. In output mode the selection of the signal routed out to a GPIO pin is
performed with the OUT_SEL register bits. The OEN bit is low active and enables the GPIO
output mode. If OUT_SEL is set to 2’b11 and the OEN bit is set to zero, the GPIO pin can be set
or reset by writing a one or zero into the STATUS location of the GPIO register. All other
To read the external status of a GPIO pin, the OEN needs to be set to one to avoid conflicts with
signals routed out of the chip. If GPIO_IN_EN4 is set to one, the status of the GPIO pin can be
monitored by reading the STATUS bit of the appropriate GPIO register. The function of all
relevant GPIO_IN/OUT signals are listed in Figure 20 and Table 16.
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