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參數資料
| 型號： | 935269580557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | PLASTIC, HTQFP-100 |
| 文件頁數： | 43/84頁 |
| 文件大小： | 1054K |
| 代理商： | 935269580557 |
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Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved.
9397 750 08865
48 of 84
Rev. 02 — 8 October 2001
Product data
PNX8510/11
Philips Semiconductors
Analog Companion Chip
10.
Audio/Clock Address Space
Bits
Read/
Write
Reset
Value
Name
(Field or Function)
Description
Offset 0000
CLK_AUDIO
7:1
-
Unused
0
R/W
0
CLK_AUDIO
0= I2S is in slave mode.
1= I2S is in master mode.
Offset 0001
CLK_IF Video Interface Clock
7:5
-
Unused
4
R/W
0
CLK_IF_DIV8
0 = default (divide by 4).
1 = divide by 8.
3
R/W
0
CLK_IF_DIV6
0 = default (divide by 3).
1 = divide by 6.
2:1
R/W
0x0
CLK_IF_DIV
00= clk_if is input video clock divide by 1 (feed through).
01= clk_if is input video clock divide by 2.
10= clk_if is input video clock divide by 3/6.
11= clk_if is input video clock divide by 4/8.
0
R/W
0
CLK_IF_EN
0 = Normal functional mode
1 = Set the clock to zero.
Offset 0002
CLK_PROC_DIV Video Processing Clock
7:5
-
Unused
4
R/W
0
CLK_PROC_DIV8
0 = Divide by 4.
1 = Divide by 8.
3
R/W
0
CLK_PROC_DIV6
0 = Default (div.ide by 3).
1 = Divide by 6
2:1
R/W
0x0
CLK_PROC_DIV
00 = clk_proc is input video clock divide by 1 (feed through).
01 = clk_proc is input video clock divide by 2.
10 = clk_proc is input video clock divide by 3/6.
11 = clk_proc is input video clock divide by 4/8.
0
R/W
0
CLK_PROC_EN
0 = Normal functional mode
1 = Set the clock to zero.
Bits
Read/
Write
Reset
Value
Name
(Field or Function)
Description
Offset 00F4
I2S_SET_REG
7:4
-
Unused
3:0
R/W
0
i2s_format
0000
/ Philips I2S
0001
/ LSB justified 16 bits
0010
/ LSB justified 18 bits
0011
/ LSB justified 20 bits
0100
/ MSB
1000
/ LSB justified 24 bits
All other combinations are reserved for future use.
Offset 00F5(LSBs)—00FB(MSBs) FEATURE_REG
54:47
-
Unused
46:39
-
Unused
38:36
-
Unused
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