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參數資料
| 型號： | 935269580557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | PLASTIC, HTQFP-100 |
| 文件頁數： | 78/84頁 |
| 文件大小： | 1054K |
| 代理商： | 935269580557 |
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Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved.
9397 750 08865
8 of 84
Rev. 02 — 8 October 2001
Product data
PNX8510/11
Philips Semiconductors
Analog Companion Chip
2.3 Video Input Module
The video input module is responsible for accommodating all supported video data formats. It
delivers a de-multiplexed and de-sliced data stream to the video processing modules.
As depicted in Figure 10, the IC has two video input ports which can accommodate 8 or 10-bit
wide video data streams.
The normal mode of operation is that the DV1 interface is routed to the primary video data paths
and the DV2 interface is routed to the secondary video data paths. The IC however accepts also
so called sliced data formats. A sliced data format contains two single video data streams
multiplexed together on a component basis. A more detailed description of the arrangement of
the components can be found in Section 2.2 Video Input Modes. To enable sliced data formats
the SLICE_MODE bit has to be set.
The De-Slice module essentially takes the two data streams apart by simply two to one de-
multiplexing. The routing of the resulting two video data streams is determined by setting the
SEL register bits in the primary and secondary video data path apertures appropriately. Sliced
data formats come in two different flavors: double edge and qualified.
The double edge slice format has data changes on the positive and the negative clock edge
where as the qualified mode qualifies one data stream of the two multiplexed ones with an active
high on the HSYNC signal. To use this mode the USE_QUALIFIER bit must be set. The order of
the slice qualification can be changed by setting the INV_QUALIFIER bit.
Since each of the video input interfaces can accept sliced data formats a total of four video data
streams could be routed into the IC and two of them can be selected to be forwarded to the
primary and the secondary video display pipeline.
Note: If the two video pipelines are sourced by only one video input interface operating in sliced
mode, both video pipelines must receive the same input clock originating from the sliced data
source.
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