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參數資料
| 型號： | 935269580557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | PLASTIC, HTQFP-100 |
| 文件頁數： | 40/84頁 |
| 文件大小： | 1054K |
| 代理商： | 935269580557 |
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Philips Semiconductors
PNX8510/11
Analog Companion Chip
9397 750 08865
Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved.
Product data
Rev. 02 — 8 October 2001
45 of 84
0
R/W
0
PD
Power down mode for DACs; powers all analog circuitry
primary video channel: DAC1-4
secondary video channel: DAC5-6
Offset 0xA6
HDCTRL - Not present in secondary video channel.
7
R/W
0
Y_TOCO
Y Two’s complement <-> binary offset conversion
0 = Data at the output of the HD-data path are left unchanged
1 = MSB of data output of the HD-data path is inverted
6
R/W
0
U_TOCO
U Two’s complement <-> binary offset conversion
0 = Data at the output of the HD-data path are left unchanged.
1 = MSB of data output of the HD-data path is inverted.
5
R/W
0
V_TOCO
V Two’s complement <-> binary offset conversion
0 = Data at the output of the HD-data path are left unchanged.
1 = MSB of data output of the HD-data path is inverted.
4
R/W
0
Y/R_SYNC_INS_EN
Enables insertion of R/Y sync signals into the component signals.
0 = Embedded sync is disabled.
1 = Embedded sync is enabled.
3
R/W
0
U/G_SYNC_INS_EN
Enables insertion of G/U sync signals into the component signals.
0 = Embedded sync is disabled.
1 = Embedded sync is enabled.
2
R/W
0
V/B_SYNC_INS_EN
Enables insertion of B/V sync signals into the component signals.
0 = Embedded sync is disabled.
1 = Embedded sync is enabled.
1
R/W
0
SYNC_SIG_EN
Sync signal insertion enable
0 = No insertion of HD sync module generated sync signals - the
external signals are forwarded to the sync pouts.
1 = The insertion of HD sync module generated H-sync, V-sync
and Blank signals is enabled. (Note: This disables external sync
signals.)
H-sync is derived from sync value[0].
V-sync is derived from sync value[1].
C-blank is derived from sync value[2].
0
R/W
0
UPSAMPLE_EN
Enable 422 to 444 upsampling filter
0 = Filter switched into bypass mode
1 = Filter is active.
Offset 0xA6
DAC6_ADJ - Not present in primary video channel.
7:5
-
Unused
4:0
R/W
0
DAC6_ADJ
DAC6 output level coarse adjustment
Offset 0xA7
DAC5_ADJ - Not present in primary video channel.
7:5
-
Unused
4:0
R/W
0
DAC5_ADJ
DAC5 output level coarse adjustment
Offset 0xA8
DACC_ADJ - Not present in primary video channel.
7:4
-
Unused
3:0
R/W
0
DACC_ADJ
DAC5 and 6 output level fine adjustment
Offset 0xA7
SYNC_DELAY
7
0
VBIPROG
0 = Programming via VBI disabled (use this mode for 24-bit parallel
mode and any other mode containing non-656 compliant data).
1 = Programming via VBI enabled
6:3
-
Unused
2:0
1
SYNC_DELAY
Determines the sync-data delay for the incoming data stream and
the associated H/V sync and Blank signals.
*Not present in secondary video channel.
Bits
Read/
Write
Reset
Value
Name
(Field or Function)
Description
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