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參數資料
| 型號： | 935269580557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | PLASTIC, HTQFP-100 |
| 文件頁數： | 84/84頁 |
| 文件大小： | 1054K |
| 代理商： | 935269580557 |
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Philips Semiconductors
PNX8510/11
Analog Companion Chip
9397 750 08865
Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved.
Product data
Rev. 02 — 8 October 2001
9 of 84
The structure of the video input module is shown in the block diagram below.
2.4 Video DAC Control
The PNX8510/11 contains 6 video DACs. Four of them are dedicated to the primary video
pipeline and the remaining 2 are assigned to the secondary video processing path.
The first DAC of the primary video channel (VOUT1) is always assigned to the primary standard
definition data path. The output of the DAC can be changed from CVBS to Y by resetting the
DAC control bit CVBSEN to zero.
The second DAC of the primary video channel (VOUT2) is either assigned to the standard
definition data path and carries the chrominance (Y/C operation) if the CEN bit in the DAC
control register is set or the Red/V channel (RGB/Component mode operation) if the DAC
control register bit CEN is reset. In HD mode (SD_HD bit set to zero) this DAC carries either the
Red channel or the Y channel depending on whether the HD path is operated in YUV or RGB
mode. Note that the CEN bit must be reset for HD operation.
Figure 10: Block Diagram of the Video Input Module
RST SYNC
Primary
Secondary
Register Array Primary
DE-SLICE
SAV-EAV
Detection
SAV-EAV
Detection
Output
Formatter
OUT-SEL
D1-IN Primary
D1-IN Secondary
R/Y/Y
G/U/U-V
B/V
Y
U-V
8/10-bit Mode
SLICE_MODE
SLICE_DIR
SLICE_MODE
SLICE_DIR
SEL1
SEL2
DEMUX_MODE
O_E
VBI Data Slicer
TTX Data Port
Output
Formatter
VBI Data Slicer
Register Array Secondary
TTX Data Port
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