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參數(shù)資料
| 型號： | 935269580557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | PLASTIC, HTQFP-100 |
| 文件頁數(shù)： | 30/84頁 |
| 文件大小： | 1054K |
| 代理商： | 935269580557 |
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Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved.
9397 750 08865
36 of 84
Rev. 02 — 8 October 2001
Product data
PNX8510/11
Philips Semiconductors
Analog Companion Chip
Registers 0x3B through 0x53 must be initialized to zero.
4
R/W
0
DEDGE
Double edge mode
0 = Double edge mode off; either the interface is running at 2x
speed to get interleaved data in or only non-interleaved data
streams are accepted.
1 = Input data is latched at positive and negative edge. The
SLICE_DIR register determines which data slice goes in which
channel.
3
R/W
1
SD_HD
Video mode switch
0 = HD data path in operation; encoder runs idle.
1 = SD data path in operation; encoder is in CVBS/YC or RGB
mode
*Not present in secondary video channel.
2
R/W
1
U2C
0 = Y/R data channel coming from the D1 interface left unchanged
1 = Y/R MSB of data coming from the D1 interface is inverted.
1
R/W
1
M2C
0 = U/G data channel coming from the D1 interface left unchanged
1 = U/G MSB of data coming from the D1 interface is inverted.
0
R/W
1
L2C
0 = V/B data channel coming from the D1 interface left unchanged
1 = V/B MSB of data coming from the D1 interface is inverted.
*Not present in secondary video channel.
Bits
Read/
Write
Reset
Value
Name
(Field or Function)
Description
Bits
Read/
Write
Reset
Value
Name
(Field or Function)
Description
Offset 0x54
VPS1
7
R/W
0
VPSEN
0 = Video programming system data insertion disabled
1 = Video programming system data insertion enabled
6:0
-
Unused
Offset 0x55
VPS2
7:0
R/W
-
VPSB5
Fifth byte of video programming system data
Offset 0x56
VPS3
7:0
R/W
-
VPSB11
11th byte of video programming system data
Offset 0x57
VPS4
7:0
R/W
-
VPSB12
12th byte of video programming system data
Offset 0x58
VPS5
7:0
R/W
-
VPSB13
13th byte of video programming system data
Offset 0x59
VPS6
7:0
R/W
-
VPSB14
14th byte of video programming system data
Offset 0x5A
CHPS
7:0
R/W
0x0
CHPS
Phase of encoded color subcarrier (including burst) relative to
horizontal sync. Can be adjusted in steps of 360/256 degrees.
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