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參數資料
| 型號： | 935269580557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | PLASTIC, HTQFP-100 |
| 文件頁數： | 75/84頁 |
| 文件大小： | 1054K |
| 代理商： | 935269580557 |
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Philips Semiconductors
PNX8510/11
Analog Companion Chip
9397 750 08865
Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved.
Product data
Rev. 02 — 8 October 2001
77 of 84
Programming Examples
Assuming an effective load of 75 // 75 = 37.5
, Rset = 1k, the coarse bits are set to 0 0 0 0
and the fine adjust bits are set to 0 0 0 0 0. The output will be sitting at the minimum level of
Vout = 0.579V.
For example, if Vout is set to 1 V, then the fine adjust bits should be set to 0 0 0 0 0 and the
coarse adjust bits set to 1 0 1 0 0.
Sleep and Powerdown Modes
Sleep mode occurs when all current output switches are disabled asynchronously so that
no current flows in either Iout or Idump pins i.e., IOUT = IDUMP = 0. Sleep mode allows a
rapid recovery from a low power consumption state. Each DAC can be put into sleep mode
asynchronously where IOUT = IDUMP = 0, yet still supply current flows to power the
bandgap, opmap, and other analog DAC components, including the digital logic.
Powerdown mode occurs when each DAC can be asynchronously put into zero state
current so that all current output switches are disabled. This includes current to all analog
and digital components of the DAC such as bandgap reference, opmaps, etc. In this mode
IDDD = IDDA = 0.
1
0
1
0
1
+75.1%
1
0
1
0
+78.7%
1
0
1
+82.3%
1
0
+85.9%
1
0
1
+89.5%
1
0
1
0
+93.0%
1
0
1
+96.6%
1
100
+100.2%
1
101
+103.8%
1
110
+107.4%
1
+110.9%
Table 37: Separate I2C Bits 31x21mV (Output Level: Coarse Adjustment for each DAC)
Bit Values
Vout
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